diff options
author | Bill Paul <wpaul@FreeBSD.org> | 2003-09-13 23:51:35 +0000 |
---|---|---|
committer | Bill Paul <wpaul@FreeBSD.org> | 2003-09-13 23:51:35 +0000 |
commit | c2c6548b3a08607903f853683343053c5fef94cb (patch) | |
tree | bec7908ee8158334886f1b0780c6f85248b712d0 /sys/dev/re/if_re.c | |
parent | d7b645262d5211e125c4cd8b6c8cb03e23db5e81 (diff) | |
download | src-c2c6548b3a08607903f853683343053c5fef94cb.tar.gz src-c2c6548b3a08607903f853683343053c5fef94cb.zip |
Teach the re(4) driver about the CFG2 register, which tells us whether
we're on a 32-bit/64-bit bus or not. Use this to decide if we should
set the PCI dual-address cycle enable bit in the C+ command register.
(Enabling DAC on a 32-bit bus seems to do bad things.)
Also, initialize the C+ command register early in the re_init() routine.
The documentation says this register should be configured first.
Notes
Notes:
svn path=/head/; revision=120043
Diffstat (limited to 'sys/dev/re/if_re.c')
-rw-r--r-- | sys/dev/re/if_re.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c index e439d3f282f3..4cdfe998e464 100644 --- a/sys/dev/re/if_re.c +++ b/sys/dev/re/if_re.c @@ -2076,6 +2076,19 @@ re_init(xsc) re_stop(sc); /* + * Enable C+ RX and TX mode, as well as VLAN stripping and + * RX checksum offload. Only enable dual-address cycle if + * we're on a 64-bit bus. We must configure the C+ register + * before all others. + */ + CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| + RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| + (CSR_READ_1(sc, RL_CFG2) & RL_BUSWIDTH_64BITS ? + RL_CPLUSCMD_PCI_DAC : 0)|RL_CPLUSCMD_VLANSTRIP| + (ifp->if_capenable & IFCAP_RXCSUM ? + RL_CPLUSCMD_RXCSUM_ENB : 0)); + + /* * Init our MAC address. Even though the chipset * documentation doesn't mention it, we need to enter "Config * register write enable" mode to modify the ID registers. @@ -2167,14 +2180,8 @@ re_init(xsc) CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); #endif /* - * If this is a C+ capable chip, enable C+ RX and TX mode, - * and load the addresses of the RX and TX lists into the chip. + * Load the addresses of the RX and TX lists into the chip. */ - CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| - RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| - RL_CPLUSCMD_VLANSTRIP| - (ifp->if_capenable & IFCAP_RXCSUM ? - RL_CPLUSCMD_RXCSUM_ENB : 0)); CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); |