Adjust mvs(4) to handle interrupt cause reg depending on the actual number of

channels available

- current code treats bits 4:7 in 'SATAHC interrupt mask' and 'SATAHC
  interrupt cause' as flags for SATA channels 2 and 3

- for embedded SATA controllers (SoC) these bits have been marked as reserved
  in datasheets so far, but for some new and upcoming chips they are used for
  purposes other than SATA

Submitted by:	Lukasz Plachno
Reviewed by:	mav
Obtained from:	Semihalf
MFC after:	2 weeks

1 files changed, 3 insertions, 0 deletions

diff --git a/sys/dev/mvs/mvs.h b/sys/dev/mvs/mvs.h
index 3fe106a64c44..f4e4a61f33f5 100644
--- a/sys/dev/mvs/mvs.h
+++ b/sys/dev/mvs/mvs.h
@@ -61,6 +61,9 @@
 
 #define CHIP_SOC_LED		0x2C	/* SoC LED Configuration */
 
+/* Additional mask for SoC devices with less than 4 channels */
+#define CHIP_SOC_HC0_MASK(num)	(0xff >> ((4 - (num)) * 2))
+
 /* Chip CCC registers */
 #define CHIP_ICC		0x18008
 #define CHIP_ICC_ALL_PORTS	 (1 << 4)	/* all ports irq event */