diff options
| author | Hans Petter Selasky <hselasky@FreeBSD.org> | 2023-04-18 11:21:28 +0000 |
|---|---|---|
| committer | Hans Petter Selasky <hselasky@FreeBSD.org> | 2023-04-18 13:01:06 +0000 |
| commit | 273bfac08ff838786c8b48bc7d3d7180b5f6a3be (patch) | |
| tree | 084fde2b5ba5e7f3a4deaf736cb53dba820d41d0 /sys/dev/mlx5/mlx5_core | |
| parent | 2f7e9a8a21367393b613f0f150d49009fa74dd5c (diff) | |
mlx5: Implement mlx5_core_modify_cq_by_mask().
Implement one CQ modify function supporting all firmware versions,
instead of having more variants of CQ modify.
MFC after: 1 week
Sponsored by: NVIDIA Networking
Diffstat (limited to 'sys/dev/mlx5/mlx5_core')
| -rw-r--r-- | sys/dev/mlx5/mlx5_core/mlx5_cq.c | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/sys/dev/mlx5/mlx5_core/mlx5_cq.c b/sys/dev/mlx5/mlx5_core/mlx5_cq.c index 8f873bde6073..e849663528b2 100644 --- a/sys/dev/mlx5/mlx5_core/mlx5_cq.c +++ b/sys/dev/mlx5/mlx5_core/mlx5_cq.c @@ -219,18 +219,9 @@ int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev, u16 cq_period, u16 cq_max_count) { - u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0}; - void *cqc; - - MLX5_SET(modify_cq_in, in, cqn, cq->cqn); - cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); - MLX5_SET(cqc, cqc, cq_period, cq_period); - MLX5_SET(cqc, cqc, cq_max_count, cq_max_count); - MLX5_SET(modify_cq_in, in, - modify_field_select_resize_field_select.modify_field_select.modify_field_select, - MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT); - - return mlx5_core_modify_cq(dev, cq, in, sizeof(in)); + return (mlx5_core_modify_cq_by_mask(dev, cq, + MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT, + cq_period, cq_max_count, 0, 0)); } int mlx5_core_modify_cq_moderation_mode(struct mlx5_core_dev *dev, @@ -239,19 +230,34 @@ int mlx5_core_modify_cq_moderation_mode(struct mlx5_core_dev *dev, u16 cq_max_count, u8 cq_mode) { - u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0}; + return (mlx5_core_modify_cq_by_mask(dev, cq, + MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT | MLX5_CQ_MODIFY_PERIOD_MODE, + cq_period, cq_max_count, cq_mode, 0)); +} + +int +mlx5_core_modify_cq_by_mask(struct mlx5_core_dev *dev, + struct mlx5_core_cq *cq, u32 mask, + u16 cq_period, u16 cq_max_count, u8 cq_mode, u8 cq_eqn) +{ + u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {}; void *cqc; MLX5_SET(modify_cq_in, in, cqn, cq->cqn); cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); - MLX5_SET(cqc, cqc, cq_period, cq_period); - MLX5_SET(cqc, cqc, cq_max_count, cq_max_count); - MLX5_SET(cqc, cqc, cq_period_mode, cq_mode); + if (mask & MLX5_CQ_MODIFY_PERIOD) + MLX5_SET(cqc, cqc, cq_period, cq_period); + if (mask & MLX5_CQ_MODIFY_COUNT) + MLX5_SET(cqc, cqc, cq_max_count, cq_max_count); + if (mask & MLX5_CQ_MODIFY_PERIOD_MODE) + MLX5_SET(cqc, cqc, cq_period_mode, cq_mode); + if (mask & MLX5_CQ_MODIFY_EQN) + MLX5_SET(cqc, cqc, c_eqn, cq_eqn); + MLX5_SET(modify_cq_in, in, - modify_field_select_resize_field_select.modify_field_select.modify_field_select, - MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT | MLX5_CQ_MODIFY_PERIOD_MODE); + modify_field_select_resize_field_select.modify_field_select.modify_field_select, mask); - return mlx5_core_modify_cq(dev, cq, in, sizeof(in)); + return (mlx5_core_modify_cq(dev, cq, in, sizeof(in))); } int mlx5_init_cq_table(struct mlx5_core_dev *dev) |