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author | Eric Joyner <erj@FreeBSD.org> | 2016-05-12 18:22:12 +0000 |
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committer | Eric Joyner <erj@FreeBSD.org> | 2016-05-12 18:22:12 +0000 |
commit | d4683565fd0673f8f140afb297bbcd7a1959ced0 (patch) | |
tree | 8fa96eace77a47b4dd0d0d875173a8af89a05410 /sys/dev/ixl/i40e_common.c | |
parent | 6d011ad5f677a2d2c99eb1d848089000ea3f463c (diff) | |
download | src-d4683565fd0673f8f140afb297bbcd7a1959ced0.tar.gz src-d4683565fd0673f8f140afb297bbcd7a1959ced0.zip |
ixl: Update to 1.4.27-k.
Changes:
Kevin Scott i40e-shared: Save off VSI resource count when updating VSI
Anjali Singhai Jain i40e-shared: Expose some registers to program parser, FD and RSS logic
Eric Joyner ixl: Fix errors in queue interrupt setup in MSIX mode.
Shannon Nelson i40e-shared: implement and use rx ctl helper functions
Shannon Nelson i40e-shared: don't use AQ calls from clear_hw
Eric Joyner ixl: Use rx ctl read/write functions instead of register accesses in certain places.
Shannon Nelson i40e-shared: add adminq commands for rx ctl registers
Shannon Nelson i40e-shared: implement and use rx ctl helper functions
Jeremiah Kyle i40e-shared: Corrected function name in comment block
Deepthi Kavalur i40e-shared: correcting a HW capability display info
Shannon Nelson i40e-shared: fixups for (Linux) upstream consistency
Eric Joyner ixl: Only stop firmware's LLDP agent on older firmware versions.
Differential Revision: https://reviews.freebsd.org/D6211
Reviewed by: sbruno, kmacy, jeffrey.e.pieper@intel.com
MFC after: 2 weeks
Sponsored by: Intel Corporation
Notes
Notes:
svn path=/head/; revision=299555
Diffstat (limited to 'sys/dev/ixl/i40e_common.c')
-rw-r--r-- | sys/dev/ixl/i40e_common.c | 136 |
1 files changed, 132 insertions, 4 deletions
diff --git a/sys/dev/ixl/i40e_common.c b/sys/dev/ixl/i40e_common.c index df7bd7c225af..5a8a8aec73ff 100644 --- a/sys/dev/ixl/i40e_common.c +++ b/sys/dev/ixl/i40e_common.c @@ -2257,6 +2257,9 @@ enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, struct i40e_aq_desc desc; struct i40e_aqc_add_get_update_vsi *cmd = (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; + struct i40e_aqc_add_get_update_vsi_completion *resp = + (struct i40e_aqc_add_get_update_vsi_completion *) + &desc.params.raw; enum i40e_status_code status; i40e_fill_default_direct_cmd_desc(&desc, @@ -2268,6 +2271,9 @@ enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, sizeof(vsi_ctx->info), cmd_details); + vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); + vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); + return status; } @@ -3507,7 +3513,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, p->num_msix_vectors = number; i40e_debug(hw, I40E_DEBUG_INIT, "HW Capability: MSIX vector count = %d\n", - p->num_msix_vectors_vf); + p->num_msix_vectors); break; case I40E_AQ_CAP_ID_VF_MSIX: p->num_msix_vectors_vf = number; @@ -4241,7 +4247,7 @@ enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, } /** - * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port + * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port * @hw: pointer to the hw struct * @flags: component flags * @mac_seid: uplink seid (MAC SEID) @@ -5077,7 +5083,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, return ret; /* Read the PF Queue Filter control register */ - val = rd32(hw, I40E_PFQF_CTL_0); + val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); /* Program required PE hash buckets for the PF */ val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; @@ -5114,7 +5120,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, if (settings->enable_macvlan) val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; - wr32(hw, I40E_PFQF_CTL_0, val); + i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); return I40E_SUCCESS; } @@ -6039,6 +6045,128 @@ restore_config: } /** + * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register + * @hw: pointer to the hw struct + * @reg_addr: register address + * @reg_val: ptr to register value + * @cmd_details: pointer to command details structure or NULL + * + * Use the firmware to read the Rx control register, + * especially useful if the Rx unit is under heavy pressure + **/ +enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, + u32 reg_addr, u32 *reg_val, + struct i40e_asq_cmd_details *cmd_details) +{ + struct i40e_aq_desc desc; + struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = + (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; + enum i40e_status_code status; + + if (reg_val == NULL) + return I40E_ERR_PARAM; + + i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); + + cmd_resp->address = CPU_TO_LE32(reg_addr); + + status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); + + if (status == I40E_SUCCESS) + *reg_val = LE32_TO_CPU(cmd_resp->value); + + return status; +} + +/** + * i40e_read_rx_ctl - read from an Rx control register + * @hw: pointer to the hw struct + * @reg_addr: register address + **/ +u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) +{ + enum i40e_status_code status = I40E_SUCCESS; + bool use_register; + int retry = 5; + u32 val = 0; + + use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); + if (!use_register) { +do_retry: + status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); + if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { + i40e_msec_delay(1); + retry--; + goto do_retry; + } + } + + /* if the AQ access failed, try the old-fashioned way */ + if (status || use_register) + val = rd32(hw, reg_addr); + + return val; +} + +/** + * i40e_aq_rx_ctl_write_register + * @hw: pointer to the hw struct + * @reg_addr: register address + * @reg_val: register value + * @cmd_details: pointer to command details structure or NULL + * + * Use the firmware to write to an Rx control register, + * especially useful if the Rx unit is under heavy pressure + **/ +enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, + u32 reg_addr, u32 reg_val, + struct i40e_asq_cmd_details *cmd_details) +{ + struct i40e_aq_desc desc; + struct i40e_aqc_rx_ctl_reg_read_write *cmd = + (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; + enum i40e_status_code status; + + i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); + + cmd->address = CPU_TO_LE32(reg_addr); + cmd->value = CPU_TO_LE32(reg_val); + + status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); + + return status; +} + +/** + * i40e_write_rx_ctl - write to an Rx control register + * @hw: pointer to the hw struct + * @reg_addr: register address + * @reg_val: register value + **/ +void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) +{ + enum i40e_status_code status = I40E_SUCCESS; + bool use_register; + int retry = 5; + + use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); + if (!use_register) { +do_retry: + status = i40e_aq_rx_ctl_write_register(hw, reg_addr, + reg_val, NULL); + if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { + i40e_msec_delay(1); + retry--; + goto do_retry; + } + } + + /* if the AQ access failed, try the old-fashioned way */ + if (status || use_register) + wr32(hw, reg_addr, reg_val); +} + +/** * i40e_aq_send_msg_to_pf * @hw: pointer to the hardware structure * @v_opcode: opcodes for VF-PF communication |