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authorWarner Losh <imp@FreeBSD.org>2009-03-31 01:59:47 +0000
committerWarner Losh <imp@FreeBSD.org>2009-03-31 01:59:47 +0000
commitf16f1caffcc44f8d4c335541e2fc8a42f091bc9f (patch)
treec1d5b2e7af3c1df341051843303943f0c21f4da0 /sys/dev/ed
parent9cf4fe2ebe5e7790a18b2b27f5c68b2b08ee34b7 (diff)
downloadsrc-f16f1caffcc44f8d4c335541e2fc8a42f091bc9f.tar.gz
src-f16f1caffcc44f8d4c335541e2fc8a42f091bc9f.zip
Hmmmm... This can't be right... But it looks like the DL100xx chips
don't have one of the clock cycles (the turn cycle) that the AX88x90 chips have. Make this conditional. But this seems totally crazy and can't possibly be right. Commit the fix for the moment until I can explore this mystery more deeply. On the plus side, the DL10022-based cards I have (D-Link DEF-670TXD and SMC8040TX) work after this fix.
Notes
Notes: svn path=/head/; revision=190583
Diffstat (limited to 'sys/dev/ed')
-rw-r--r--sys/dev/ed/if_ed_pccard.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/sys/dev/ed/if_ed_pccard.c b/sys/dev/ed/if_ed_pccard.c
index 05c5c07cfbb1..924cc833adbe 100644
--- a/sys/dev/ed/if_ed_pccard.c
+++ b/sys/dev/ed/if_ed_pccard.c
@@ -1115,7 +1115,9 @@ ed_miibus_readreg(device_t dev, int phy, int reg)
(*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
(*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
(*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
- (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
+ if (sc->chip_type == ED_CHIP_TYPE_AX88790 ||
+ sc->chip_type == ED_CHIP_TYPE_AX88190)
+ (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
(*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);