aboutsummaryrefslogtreecommitdiff
path: root/sys/dev/drm2
diff options
context:
space:
mode:
authorEitan Adler <eadler@FreeBSD.org>2013-11-30 22:17:27 +0000
committerEitan Adler <eadler@FreeBSD.org>2013-11-30 22:17:27 +0000
commit7a22215c5346c9009d1dfa4d3c118ff99f89d184 (patch)
tree050fb3b68519f6ef7d59051550fa29cdd79d6dac /sys/dev/drm2
parentc8aef31d309ac3f874c461619248fee9c1d74c2f (diff)
downloadsrc-7a22215c5346c9009d1dfa4d3c118ff99f89d184.tar.gz
src-7a22215c5346c9009d1dfa4d3c118ff99f89d184.zip
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the expected result. This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD. Discussed with: -arch, rdivacky Reviewed by: cperciva
Notes
Notes: svn path=/head/; revision=258780
Diffstat (limited to 'sys/dev/drm2')
-rw-r--r--sys/dev/drm2/i915/i915_reg.h44
-rw-r--r--sys/dev/drm2/radeon/evergreen_blit_kms.c4
-rw-r--r--sys/dev/drm2/radeon/evergreen_cs.c12
-rw-r--r--sys/dev/drm2/radeon/evergreend.h22
-rw-r--r--sys/dev/drm2/radeon/nid.h10
-rw-r--r--sys/dev/drm2/radeon/r200.c2
-rw-r--r--sys/dev/drm2/radeon/r300.c2
-rw-r--r--sys/dev/drm2/radeon/r300_reg.h6
-rw-r--r--sys/dev/drm2/radeon/r500_reg.h8
-rw-r--r--sys/dev/drm2/radeon/r600_blit.c4
-rw-r--r--sys/dev/drm2/radeon/r600_blit_kms.c4
-rw-r--r--sys/dev/drm2/radeon/r600_cs.c2
-rw-r--r--sys/dev/drm2/radeon/r600d.h16
-rw-r--r--sys/dev/drm2/radeon/radeon_cp.c2
-rw-r--r--sys/dev/drm2/radeon/radeon_drv.h30
-rw-r--r--sys/dev/drm2/radeon/radeon_reg.h36
-rw-r--r--sys/dev/drm2/radeon/rv770d.h8
-rw-r--r--sys/dev/drm2/radeon/sid.h18
-rw-r--r--sys/dev/drm2/ttm/ttm_bo.c6
19 files changed, 118 insertions, 118 deletions
diff --git a/sys/dev/drm2/i915/i915_reg.h b/sys/dev/drm2/i915/i915_reg.h
index 7c8dedcd84ee..8cb6fbaecb03 100644
--- a/sys/dev/drm2/i915/i915_reg.h
+++ b/sys/dev/drm2/i915/i915_reg.h
@@ -798,7 +798,7 @@ __FBSDID("$FreeBSD$");
#define _DPLL_A 0x06014
#define _DPLL_B 0x06018
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
-#define DPLL_VCO_ENABLE (1 << 31)
+#define DPLL_VCO_ENABLE (1U << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30)
#define DPLL_SYNCLOCK_ENABLE (1 << 29)
#define DPLL_VGA_MODE_DIS (1 << 28)
@@ -1483,7 +1483,7 @@ __FBSDID("$FreeBSD$");
/* SDVO port control */
#define SDVOB 0x61140
#define SDVOC 0x61160
-#define SDVO_ENABLE (1 << 31)
+#define SDVO_ENABLE (1U << 31)
#define SDVO_PIPE_B_SELECT (1 << 30)
#define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26)
@@ -1521,7 +1521,7 @@ __FBSDID("$FreeBSD$");
#define DVOA 0x61120
#define DVOB 0x61140
#define DVOC 0x61160
-#define DVO_ENABLE (1 << 31)
+#define DVO_ENABLE (1U << 31)
#define DVO_PIPE_B_SELECT (1 << 30)
#define DVO_PIPE_STALL_UNUSED (0 << 28)
#define DVO_PIPE_STALL (1 << 28)
@@ -1557,7 +1557,7 @@ __FBSDID("$FreeBSD$");
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe.
*/
-#define LVDS_PORT_EN (1 << 31)
+#define LVDS_PORT_EN (1U << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */
#define LVDS_PIPEB_SELECT (1 << 30)
#define LVDS_PIPE_MASK (1 << 30)
@@ -1604,7 +1604,7 @@ __FBSDID("$FreeBSD$");
/* Video Data Island Packet control */
#define VIDEO_DIP_DATA 0x61178
#define VIDEO_DIP_CTL 0x61170
-#define VIDEO_DIP_ENABLE (1 << 31)
+#define VIDEO_DIP_ENABLE (1U << 31)
#define VIDEO_DIP_PORT_B (1 << 29)
#define VIDEO_DIP_PORT_C (2 << 29)
#define VIDEO_DIP_ENABLE_AVI (1 << 21)
@@ -1620,7 +1620,7 @@ __FBSDID("$FreeBSD$");
/* Panel power sequencing */
#define PP_STATUS 0x61200
-#define PP_ON (1 << 31)
+#define PP_ON (1U << 31)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -1653,7 +1653,7 @@ __FBSDID("$FreeBSD$");
/* Panel fitting */
#define PFIT_CONTROL 0x61230
-#define PFIT_ENABLE (1 << 31)
+#define PFIT_ENABLE (1U << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
#define VERT_INTERP_DISABLE (0 << 10)
@@ -1714,7 +1714,7 @@ __FBSDID("$FreeBSD$");
/* TV port control */
#define TV_CTL 0x68000
/** Enables the TV encoder */
-# define TV_ENC_ENABLE (1 << 31)
+# define TV_ENC_ENABLE (1U << 31)
/** Sources the TV encoder input from pipe B instead of A. */
# define TV_ENC_PIPEB_SELECT (1 << 30)
/** Outputs composite video (DAC A only) */
@@ -1786,7 +1786,7 @@ __FBSDID("$FreeBSD$");
*
* This gets cleared when TV_DAC_STATE_EN is cleared
*/
-# define TVDAC_STATE_CHG (1 << 31)
+# define TVDAC_STATE_CHG (1U << 31)
# define TVDAC_SENSE_MASK (7 << 28)
/** Reports that DAC A voltage is above the detect threshold */
# define TVDAC_A_SENSE (1 << 30)
@@ -1913,7 +1913,7 @@ __FBSDID("$FreeBSD$");
#define TV_H_CTL_2 0x68034
/** Enables the colorburst (needed for non-component color) */
-# define TV_BURST_ENA (1 << 31)
+# define TV_BURST_ENA (1U << 31)
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
# define TV_HBURST_START_SHIFT 16
# define TV_HBURST_START_MASK 0x1fff0000
@@ -1958,7 +1958,7 @@ __FBSDID("$FreeBSD$");
#define TV_V_CTL_3 0x68044
/** Enables generation of the equalization signal */
-# define TV_EQUAL_ENA (1 << 31)
+# define TV_EQUAL_ENA (1U << 31)
/** Length of vsync, in half lines */
# define TV_VEQ_LEN_MASK 0x007f0000
# define TV_VEQ_LEN_SHIFT 16
@@ -2032,7 +2032,7 @@ __FBSDID("$FreeBSD$");
#define TV_SC_CTL_1 0x68060
/** Turns on the first subcarrier phase generation DDA */
-# define TV_SC_DDA1_EN (1 << 31)
+# define TV_SC_DDA1_EN (1U << 31)
/** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA2_EN (1 << 30)
/** Turns on the first subcarrier phase generation DDA */
@@ -2095,7 +2095,7 @@ __FBSDID("$FreeBSD$");
* If set, the rest of the registers are ignored, and the calculated values can
* be read back from the register.
*/
-# define TV_AUTO_SCALE (1 << 31)
+# define TV_AUTO_SCALE (1U << 31)
/**
* Disables the vertical filter.
*
@@ -2158,7 +2158,7 @@ __FBSDID("$FreeBSD$");
# define TV_VSCALE_IP_FRAC_SHIFT 0
#define TV_CC_CONTROL 0x68090
-# define TV_CC_ENABLE (1 << 31)
+# define TV_CC_ENABLE (1U << 31)
/**
* Specifies which field to send the CC data in.
*
@@ -2174,7 +2174,7 @@ __FBSDID("$FreeBSD$");
# define TV_CC_LINE_SHIFT 0
#define TV_CC_DATA 0x68094
-# define TV_CC_RDY (1 << 31)
+# define TV_CC_RDY (1U << 31)
/** Second word of CC data to be transmitted. */
# define TV_CC_DATA_2_MASK 0x007f0000
# define TV_CC_DATA_2_SHIFT 16
@@ -2197,7 +2197,7 @@ __FBSDID("$FreeBSD$");
#define DP_C 0x64200
#define DP_D 0x64300
-#define DP_PORT_EN (1 << 31)
+#define DP_PORT_EN (1U << 31)
#define DP_PIPEB_SELECT (1 << 30)
#define DP_PIPE_MASK (1 << 30)
@@ -2307,7 +2307,7 @@ __FBSDID("$FreeBSD$");
#define DPD_AUX_CH_DATA4 0x64320
#define DPD_AUX_CH_DATA5 0x64324
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
+#define DP_AUX_CH_CTL_SEND_BUSY (1U << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
@@ -2903,7 +2903,7 @@ __FBSDID("$FreeBSD$");
/* VBIOS regs */
#define VGACNTRL 0x71400
-# define VGA_DISP_DISABLE (1 << 31)
+# define VGA_DISP_DISABLE (1U << 31)
# define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29)
@@ -3029,7 +3029,7 @@ __FBSDID("$FreeBSD$");
#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */
-#define DE_MASTER_IRQ_CONTROL (1 << 31)
+#define DE_MASTER_IRQ_CONTROL (1U << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
#define DE_SPRITEA_FLIP_DONE (1 << 28)
#define DE_PLANEB_FLIP_DONE (1 << 27)
@@ -3553,7 +3553,7 @@ __FBSDID("$FreeBSD$");
/* or SDVOB */
#define HDMIB 0xe1140
-#define PORT_ENABLE (1 << 31)
+#define PORT_ENABLE (1U << 31)
#define TRANSCODER(pipe) ((pipe) << 30)
#define TRANSCODER_CPT(pipe) ((pipe) << 29)
#define TRANSCODER_MASK (1 << 30)
@@ -3583,13 +3583,13 @@ __FBSDID("$FreeBSD$");
#define LVDS_DETECTED (1 << 1)
#define BLC_PWM_CPU_CTL2 0x48250
-#define PWM_ENABLE (1 << 31)
+#define PWM_ENABLE (1U << 31)
#define PWM_PIPE_A (0 << 29)
#define PWM_PIPE_B (1 << 29)
#define BLC_PWM_CPU_CTL 0x48254
#define BLC_PWM_PCH_CTL1 0xc8250
-#define PWM_PCH_ENABLE (1 << 31)
+#define PWM_PCH_ENABLE (1U << 31)
#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
diff --git a/sys/dev/drm2/radeon/evergreen_blit_kms.c b/sys/dev/drm2/radeon/evergreen_blit_kms.c
index 1012f3f35f34..f89f8b5bb31c 100644
--- a/sys/dev/drm2/radeon/evergreen_blit_kms.c
+++ b/sys/dev/drm2/radeon/evergreen_blit_kms.c
@@ -241,12 +241,12 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
- radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
+ radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
- radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
+ radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
}
diff --git a/sys/dev/drm2/radeon/evergreen_cs.c b/sys/dev/drm2/radeon/evergreen_cs.c
index 693c38c29007..1dac26548613 100644
--- a/sys/dev/drm2/radeon/evergreen_cs.c
+++ b/sys/dev/drm2/radeon/evergreen_cs.c
@@ -2949,7 +2949,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
switch (misc) {
case 0:
/* L2T, frame to fields */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
return -EINVAL;
}
@@ -2992,7 +2992,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
return -EINVAL;
}
/* detile bit */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
@@ -3009,7 +3009,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
break;
case 3:
/* L2T, broadcast */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
@@ -3048,7 +3048,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
case 4:
/* L2T, T2L */
/* detile bit */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
@@ -3093,7 +3093,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
break;
case 7:
/* L2T, broadcast */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
@@ -3137,7 +3137,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
switch (misc) {
case 0:
/* detile bit */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
diff --git a/sys/dev/drm2/radeon/evergreend.h b/sys/dev/drm2/radeon/evergreend.h
index 3fd74ce1e491..044351ad2930 100644
--- a/sys/dev/drm2/radeon/evergreend.h
+++ b/sys/dev/drm2/radeon/evergreend.h
@@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
#define INSTANCE_INDEX(x) ((x) << 0)
#define SE_INDEX(x) ((x) << 16)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
-#define SE_BROADCAST_WRITES (1 << 31)
+#define SE_BROADCAST_WRITES (1U << 31)
#define RLC_GFX_INDEX 0x3fC4
#define CC_GC_SHADER_PIPE_CONFIG 0x8950
#define WRITE_DIS (1 << 0)
@@ -125,7 +125,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
@@ -187,7 +187,7 @@ __FBSDID("$FreeBSD$");
# define HDMI_ACR_X1 1
# define HDMI_ACR_X2 2
# define HDMI_ACR_X4 4
-# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)
+# define HDMI_ACR_AUDIO_PRIORITY (1U << 31)
#define HDMI_VBI_PACKET_CONTROL 0x7040
# define HDMI_NULL_SEND (1 << 0)
# define HDMI_GC_SEND (1 << 4)
@@ -322,7 +322,7 @@ __FBSDID("$FreeBSD$");
# define AFMT_AUDIO_CRC_EN (1 << 0)
#define AFMT_RAMP_CONTROL0 0x7110
# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
-# define AFMT_RAMP_DATA_SIGN (1 << 31)
+# define AFMT_RAMP_DATA_SIGN (1U << 31)
#define AFMT_RAMP_CONTROL1 0x7114
# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
@@ -406,7 +406,7 @@ __FBSDID("$FreeBSD$");
# define PIN1_AUDIO_ENABLED (1 << 25)
# define PIN2_AUDIO_ENABLED (1 << 26)
# define PIN3_AUDIO_ENABLED (1 << 27)
-# define AUDIO_ENABLED (1 << 31)
+# define AUDIO_ENABLED (1U << 31)
#define GC_USER_SHADER_PIPE_CONFIG 0x8954
@@ -452,7 +452,7 @@ __FBSDID("$FreeBSD$");
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
-#define GUI_ACTIVE (1 << 31)
+#define GUI_ACTIVE (1U << 31)
#define GRBM_STATUS_SE0 0x8014
#define GRBM_STATUS_SE1 0x8018
#define SE_SX_CLEAN (1 << 0)
@@ -464,7 +464,7 @@ __FBSDID("$FreeBSD$");
#define SE_SH_BUSY (1 << 28)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
-#define SE_CB_BUSY (1 << 31)
+#define SE_CB_BUSY (1U << 31)
/* evergreen */
#define CG_THERMAL_CTRL 0x72c
#define TOFFSET_MASK 0x00003FE0
@@ -771,7 +771,7 @@ __FBSDID("$FreeBSD$");
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
-# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
+# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@@ -797,13 +797,13 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_ENABLE (1 << 26)
# define IB2_INT_ENABLE (1 << 29)
# define IB1_INT_ENABLE (1 << 30)
-# define RB_INT_ENABLE (1 << 31)
+# define RB_INT_ENABLE (1U << 31)
#define CP_INT_STATUS 0xc128
# define SCRATCH_INT_STAT (1 << 25)
# define TIME_STAMP_INT_STAT (1 << 26)
# define IB2_INT_STAT (1 << 29)
# define IB1_INT_STAT (1 << 30)
-# define RB_INT_STAT (1 << 31)
+# define RB_INT_STAT (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@@ -1062,7 +1062,7 @@ __FBSDID("$FreeBSD$");
* 1 - GDS
* 2 - DATA
*/
-# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
+# define PACKET3_CP_DMA_CP_SYNC (1U << 31)
/* COMMAND */
# define PACKET3_CP_DMA_DIS_WC (1 << 21)
# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
diff --git a/sys/dev/drm2/radeon/nid.h b/sys/dev/drm2/radeon/nid.h
index afe7a3286989..89c023735716 100644
--- a/sys/dev/drm2/radeon/nid.h
+++ b/sys/dev/drm2/radeon/nid.h
@@ -219,7 +219,7 @@ __FBSDID("$FreeBSD$");
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
-#define GUI_ACTIVE (1 << 31)
+#define GUI_ACTIVE (1U << 31)
#define GRBM_STATUS_SE0 0x8014
#define GRBM_STATUS_SE1 0x8018
#define SE_SX_CLEAN (1 << 0)
@@ -233,7 +233,7 @@ __FBSDID("$FreeBSD$");
#define SE_SH_BUSY (1 << 28)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
-#define SE_CB_BUSY (1 << 31)
+#define SE_CB_BUSY (1U << 31)
#define GRBM_SOFT_RESET 0x8020
#define SOFT_RESET_CP (1 << 0)
#define SOFT_RESET_CB (1 << 1)
@@ -253,7 +253,7 @@ __FBSDID("$FreeBSD$");
#define INSTANCE_INDEX(x) ((x) << 0)
#define SE_INDEX(x) ((x) << 16)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
-#define SE_BROADCAST_WRITES (1 << 31)
+#define SE_BROADCAST_WRITES (1U << 31)
#define SCRATCH_REG0 0x8500
#define SCRATCH_REG1 0x8504
@@ -442,7 +442,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB0_RPTR_ADDR 0xC10C
#define CP_RB0_RPTR_ADDR_HI 0xC110
@@ -641,7 +641,7 @@ __FBSDID("$FreeBSD$");
#define DMA_IB_CNTL 0xd024
# define DMA_IB_ENABLE (1 << 0)
# define DMA_IB_SWAP_ENABLE (1 << 4)
-# define CMD_VMID_FORCE (1 << 31)
+# define CMD_VMID_FORCE (1U << 31)
#define DMA_IB_RPTR 0xd028
#define DMA_CNTL 0xd02c
# define TRAP_ENABLE (1 << 0)
diff --git a/sys/dev/drm2/radeon/r200.c b/sys/dev/drm2/radeon/r200.c
index fe8b768046c2..566645fddb95 100644
--- a/sys/dev/drm2/radeon/r200.c
+++ b/sys/dev/drm2/radeon/r200.c
@@ -116,7 +116,7 @@ int r200_copy_dma(struct radeon_device *rdev,
radeon_ring_write(ring, PACKET0(0x720, 2));
radeon_ring_write(ring, src_offset);
radeon_ring_write(ring, dst_offset);
- radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
+ radeon_ring_write(ring, cur_size | (1U << 31) | (1 << 30));
src_offset += cur_size;
dst_offset += cur_size;
}
diff --git a/sys/dev/drm2/radeon/r300.c b/sys/dev/drm2/radeon/r300.c
index aa9073cf2700..56810354c724 100644
--- a/sys/dev/drm2/radeon/r300.c
+++ b/sys/dev/drm2/radeon/r300.c
@@ -1041,7 +1041,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].height = tmp + 1;
tmp = (idx_value >> 26) & 0xF;
track->textures[i].num_levels = tmp;
- tmp = idx_value & (1 << 31);
+ tmp = idx_value & (1U << 31);
track->textures[i].use_pitch = !!tmp;
tmp = (idx_value >> 22) & 0xF;
track->textures[i].txdepth = tmp;
diff --git a/sys/dev/drm2/radeon/r300_reg.h b/sys/dev/drm2/radeon/r300_reg.h
index 3478d00920dd..3dc2b430c797 100644
--- a/sys/dev/drm2/radeon/r300_reg.h
+++ b/sys/dev/drm2/radeon/r300_reg.h
@@ -1210,7 +1210,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI0_OUTC_FRC (9 << 23)
# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
# define R300_FPI0_OUTC_SAT (1 << 30)
-# define R300_FPI0_INSERT_NOP (1 << 31)
+# define R300_FPI0_INSERT_NOP (1U << 31)
#define R300_PFS_INSTR2_0 0x49C0
# define R300_FPI2_ARGA_SRC0C_X 0
@@ -1257,7 +1257,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI2_OUTA_RCP (10 << 23)
# define R300_FPI2_OUTA_RSQ (11 << 23)
# define R300_FPI2_OUTA_SAT (1 << 30)
-# define R300_FPI2_UNKNOWN_31 (1 << 31)
+# define R300_FPI2_UNKNOWN_31 (1U << 31)
/* END: Fragment program instruction set */
/* Fog state and color */
@@ -1460,7 +1460,7 @@ __FBSDID("$FreeBSD$");
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31)
#define R300_ZB_BW_CNTL 0x4f1c
# define R300_HIZ_DISABLE (0 << 0)
diff --git a/sys/dev/drm2/radeon/r500_reg.h b/sys/dev/drm2/radeon/r500_reg.h
index c56088b86525..7b7130ec227f 100644
--- a/sys/dev/drm2/radeon/r500_reg.h
+++ b/sys/dev/drm2/radeon/r500_reg.h
@@ -88,7 +88,7 @@ __FBSDID("$FreeBSD$");
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
-# define R300_PIPE_AUTO_CONFIG (1 << 31)
+# define R300_PIPE_AUTO_CONFIG (1U << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
@@ -148,7 +148,7 @@ __FBSDID("$FreeBSD$");
# define RS480_GTW_LAC_EN (1 << 25)
# define RS480_2LEVEL_GART (0 << 30)
# define RS480_1LEVEL_GART (1 << 30)
-# define RS480_PDC_EN (1 << 31)
+# define RS480_PDC_EN (1U << 31)
#define RS480_GART_BASE 0x2c
#define RS480_GART_CACHE_CNTRL 0x2e
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
@@ -639,7 +639,7 @@ __FBSDID("$FreeBSD$");
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31)
#define AVIVO_LVTMA_CNTL 0x7a80
# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
@@ -705,7 +705,7 @@ __FBSDID("$FreeBSD$");
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31)
#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
#define R600_LVTMA_PWRSEQ_CNTL 0x7af4
diff --git a/sys/dev/drm2/radeon/r600_blit.c b/sys/dev/drm2/radeon/r600_blit.c
index 10da7883c626..f44fd797a89f 100644
--- a/sys/dev/drm2/radeon/r600_blit.c
+++ b/sys/dev/drm2/radeon/r600_blit.c
@@ -275,12 +275,12 @@ set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
- OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+ OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
- OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+ OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
ADVANCE_RING();
}
diff --git a/sys/dev/drm2/radeon/r600_blit_kms.c b/sys/dev/drm2/radeon/r600_blit_kms.c
index e2ace6936a9f..47af99028df8 100644
--- a/sys/dev/drm2/radeon/r600_blit_kms.c
+++ b/sys/dev/drm2/radeon/r600_blit_kms.c
@@ -244,12 +244,12 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
- radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
+ radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
- radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
+ radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
}
diff --git a/sys/dev/drm2/radeon/r600_cs.c b/sys/dev/drm2/radeon/r600_cs.c
index 6ba461432668..9000b3c7d027 100644
--- a/sys/dev/drm2/radeon/r600_cs.c
+++ b/sys/dev/drm2/radeon/r600_cs.c
@@ -2664,7 +2664,7 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
if (tiled) {
idx_value = radeon_get_ib_value(p, idx + 2);
/* detile bit */
- if (idx_value & (1 << 31)) {
+ if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
diff --git a/sys/dev/drm2/radeon/r600d.h b/sys/dev/drm2/radeon/r600d.h
index 41cc7c6dd89f..174b1feda4a9 100644
--- a/sys/dev/drm2/radeon/r600d.h
+++ b/sys/dev/drm2/radeon/r600d.h
@@ -204,7 +204,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
@@ -220,7 +220,7 @@ __FBSDID("$FreeBSD$");
#define CP_SEM_WAIT_TIMER 0x85BC
#define DB_DEBUG 0x9830
-#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
+#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31)
#define DB_DEPTH_BASE 0x2800C
#define DB_HTILE_DATA_BASE 0x28014
#define DB_HTILE_SURFACE 0x28D24
@@ -507,7 +507,7 @@ __FBSDID("$FreeBSD$");
#define SYNC_WALKER (1 << 25)
#define SYNC_ALIGNER (1 << 26)
#define BILINEAR_PRECISION_6_BIT (0 << 31)
-#define BILINEAR_PRECISION_8_BIT (1 << 31)
+#define BILINEAR_PRECISION_8_BIT (1U << 31)
#define TC_CNTL 0x9608
#define TC_L2_SIZE(x) ((x)<<5)
@@ -650,7 +650,7 @@ __FBSDID("$FreeBSD$");
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
-# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
+# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@@ -701,13 +701,13 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_ENABLE (1 << 26)
# define IB2_INT_ENABLE (1 << 29)
# define IB1_INT_ENABLE (1 << 30)
-# define RB_INT_ENABLE (1 << 31)
+# define RB_INT_ENABLE (1U << 31)
#define CP_INT_STATUS 0xc128
# define SCRATCH_INT_STAT (1 << 25)
# define TIME_STAMP_INT_STAT (1 << 26)
# define IB2_INT_STAT (1 << 29)
# define IB1_INT_STAT (1 << 30)
-# define RB_INT_STAT (1 << 31)
+# define RB_INT_STAT (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@@ -914,7 +914,7 @@ __FBSDID("$FreeBSD$");
#define DCCG_AUDIO_DTO0_PHASE 0x0514
#define DCCG_AUDIO_DTO0_MODULE 0x0518
#define DCCG_AUDIO_DTO0_LOAD 0x051c
-# define DTO_LOAD (1 << 31)
+# define DTO_LOAD (1U << 31)
#define DCCG_AUDIO_DTO0_CNTL 0x0520
#define DCCG_AUDIO_DTO1_PHASE 0x0524
@@ -1197,7 +1197,7 @@ __FBSDID("$FreeBSD$");
* 5. DST_ADDR_HI [7:0]
* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
*/
-# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
+# define PACKET3_CP_DMA_CP_SYNC (1U << 31)
/* COMMAND */
# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
/* 0 - none
diff --git a/sys/dev/drm2/radeon/radeon_cp.c b/sys/dev/drm2/radeon/radeon_cp.c
index 4a036336cdbc..4ec2773fd08f 100644
--- a/sys/dev/drm2/radeon/radeon_cp.c
+++ b/sys/dev/drm2/radeon/radeon_cp.c
@@ -564,7 +564,7 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
#if 0
u32 tmp;
- tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
+ tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31);
RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
}
diff --git a/sys/dev/drm2/radeon/radeon_drv.h b/sys/dev/drm2/radeon/radeon_drv.h
index 0e210f89389b..99c6aa402b0d 100644
--- a/sys/dev/drm2/radeon/radeon_drv.h
+++ b/sys/dev/drm2/radeon/radeon_drv.h
@@ -572,7 +572,7 @@ void radeon_unregister_atpx_handler(void);
# define RS480_GTW_LAC_EN (1 << 25)
# define RS480_2LEVEL_GART (0 << 30)
# define RS480_1LEVEL_GART (1 << 30)
-# define RS480_PDC_EN (1 << 31)
+# define RS480_PDC_EN (1U << 31)
#define RS480_GART_BASE 0x2c
#define RS480_GART_CACHE_CNTRL 0x2e
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
@@ -688,7 +688,7 @@ void radeon_unregister_atpx_handler(void);
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
-# define R300_PIPE_AUTO_CONFIG (1 << 31)
+# define R300_PIPE_AUTO_CONFIG (1U << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
@@ -815,7 +815,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R300_RB2D_DC_FLUSH (3 << 0)
# define R300_RB2D_DC_FREE (3 << 2)
# define R300_RB2D_DC_FLUSH_ALL 0xf
-# define R300_RB2D_DC_BUSY (1 << 31)
+# define R300_RB2D_DC_BUSY (1U << 31)
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@@ -837,16 +837,16 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_RB3D_ZC_FLUSH (1 << 0)
# define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
-# define RADEON_RB3D_ZC_BUSY (1 << 31)
+# define RADEON_RB3D_ZC_BUSY (1U << 31)
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
-# define R300_ZC_BUSY (1 << 31)
+# define R300_ZC_BUSY (1U << 31)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
-# define RADEON_RB3D_DC_BUSY (1 << 31)
+# define RADEON_RB3D_DC_BUSY (1U << 31)
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
@@ -862,7 +862,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
-# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -916,7 +916,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
# define RADEON_GA_BUSY (1 << 26)
# define RADEON_CBA2D_BUSY (1 << 27)
-# define RADEON_RBBM_ACTIVE (1 << 31)
+# define RADEON_RBBM_ACTIVE (1U << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_MISC 0x26c4
#define RADEON_RE_TOP_LEFT 0x26c0
@@ -1030,7 +1030,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
-# define RADEON_RB_RPTR_WR_ENA (1 << 31)
+# define RADEON_RB_RPTR_WR_ENA (1U << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@@ -1166,7 +1166,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
-#define RADEON_VTX_Z_PRESENT (1 << 31)
+#define RADEON_VTX_Z_PRESENT (1U << 31)
#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
#define RADEON_PRIM_TYPE_NONE (0 << 0)
@@ -1497,7 +1497,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_GRBM_STATUS 0x8010
# define R600_CMDFIFO_AVAIL_MASK 0x1f
# define R700_CMDFIFO_AVAIL_MASK 0xf
-# define R600_GUI_ACTIVE (1 << 31)
+# define R600_GUI_ACTIVE (1U << 31)
#define R600_GRBM_STATUS2 0x8014
#define R600_GRBM_SOFT_RESET 0x8020
# define R600_SOFT_RESET_CP (1 << 0)
@@ -1520,7 +1520,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_RB_BLKSZ(x) ((x) << 8)
# define R600_BUF_SWAP_32BIT (2 << 16)
# define R600_RB_NO_UPDATE (1 << 27)
-# define R600_RB_RPTR_WR_ENA (1 << 31)
+# define R600_RB_RPTR_WR_ENA (1U << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
@@ -1593,7 +1593,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_SX_MISC 0x28350
#define R600_DB_DEBUG 0x9830
-# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
+# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31)
#define R600_DB_WATERMARKS 0x9838
# define R600_DEPTH_FREE(x) ((x) << 0)
# define R600_DEPTH_FLUSH(x) ((x) << 5)
@@ -1699,7 +1699,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_SYNC_WALKER (1 << 25)
# define R600_SYNC_ALIGNER (1 << 26)
# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
-# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
+# define R600_BILINEAR_PRECISION_8_BIT (1U << 31)
#define R700_TCP_CNTL 0x9610
@@ -1773,7 +1773,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_PERSP_GRADIENT_ENA (1 << 28)
# define R600_LINEAR_GRADIENT_ENA (1 << 29)
# define R600_POSITION_SAMPLE (1 << 30)
-# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
+# define R600_BARYC_AT_SAMPLE_ENA (1U << 31)
#define R600_SPI_PS_IN_CONTROL_1 0x286d0
# define R600_GEN_INDEX_PIX (1 << 0)
# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
diff --git a/sys/dev/drm2/radeon/radeon_reg.h b/sys/dev/drm2/radeon/radeon_reg.h
index a9dacc1979ee..22ab717f0186 100644
--- a/sys/dev/drm2/radeon/radeon_reg.h
+++ b/sys/dev/drm2/radeon/radeon_reg.h
@@ -361,7 +361,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
-# define RADEON_TVCLK_TURNOFF (1 << 31)
+# define RADEON_TVCLK_TURNOFF (1U << 31)
#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
# define RADEON_PM_MODE_SEL (1 << 13)
# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
@@ -585,13 +585,13 @@ __FBSDID("$FreeBSD$");
#define RADEON_CUR_HORZ_VERT_OFF 0x0268
#define RADEON_CUR_HORZ_VERT_POSN 0x0264
#define RADEON_CUR_OFFSET 0x0260
-# define RADEON_CUR_LOCK (1 << 31)
+# define RADEON_CUR_LOCK (1U << 31)
#define RADEON_CUR2_CLR0 0x036c
#define RADEON_CUR2_CLR1 0x0370
#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
#define RADEON_CUR2_OFFSET 0x0360
-# define RADEON_CUR2_LOCK (1 << 31)
+# define RADEON_CUR2_LOCK (1U << 31)
#define RADEON_DAC_CNTL 0x0058
# define RADEON_DAC_RANGE_CNTL (3 << 0)
@@ -670,7 +670,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TV_DAC_BDACPD (1 << 26)
# define RADEON_TV_DAC_RDACDET (1 << 29)
# define RADEON_TV_DAC_GDACDET (1 << 30)
-# define RADEON_TV_DAC_BDACDET (1 << 31)
+# define RADEON_TV_DAC_BDACDET (1U << 31)
# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
# define R420_TV_DAC_RDACPD (1 << 25)
# define R420_TV_DAC_GDACPD (1 << 26)
@@ -745,7 +745,7 @@ __FBSDID("$FreeBSD$");
#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
# define RADEON_DST_Y_MAJOR (1 << 2)
# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
-# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
+# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1U << 31)
#define RADEON_DP_DATATYPE 0x16c4
# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
#define RADEON_DP_GUI_MASTER_CNTL 0x146c
@@ -1230,7 +1230,7 @@ __FBSDID("$FreeBSD$");
#define RADEON_MIN_GRANT 0x0f3e /* PCI */
#define RADEON_MM_DATA 0x0004
#define RADEON_MM_INDEX 0x0000
-# define RADEON_MM_APER (1 << 31)
+# define RADEON_MM_APER (1U << 31)
#define RADEON_MPLL_CNTL 0x000e /* PLL */
#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
@@ -1600,12 +1600,12 @@ __FBSDID("$FreeBSD$");
# define RADEON_SOFT_RESET_HDP (1 << 7)
#define RADEON_RBBM_STATUS 0x0e40
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
-# define RADEON_RBBM_ACTIVE (1 << 31)
+# define RADEON_RBBM_ACTIVE (1U << 31)
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
# define RADEON_RB2D_DC_FLUSH (3 << 0)
# define RADEON_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
-# define RADEON_RB2D_DC_BUSY (1 << 31)
+# define RADEON_RB2D_DC_BUSY (1U << 31)
#define RADEON_RB2D_DSTCACHE_MODE 0x3428
#define RADEON_DSTCACHE_CTLSTAT 0x1714
@@ -1631,7 +1631,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
-# define RADEON_RB3D_DC_BUSY (1 << 31)
+# define RADEON_RB3D_DC_BUSY (1U << 31)
#define RADEON_REG_BASE 0x0f18 /* PCI */
#define RADEON_REGPROG_INF 0x0f09 /* PCI */
@@ -1854,7 +1854,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_WAIT_VAP_IDLE (1 << 28)
# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
-# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
+# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1U << 31)
#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
#define RADEON_XCLK_CNTL 0x000d /* PLL */
@@ -1896,7 +1896,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_BUMPED_MAP_T2 (2 << 27)
# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
-# define RADEON_MC_ENABLE (1 << 31)
+# define RADEON_MC_ENABLE (1U << 31)
#define RADEON_PP_FOG_COLOR 0x1c18
# define RADEON_FOG_COLOR_MASK 0x00ffffff
# define RADEON_FOG_VERTEX (0 << 24)
@@ -2091,7 +2091,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TEX_VSIZE_SHIFT 16
# define RADEON_SIGNED_RGB_MASK (1 << 30)
# define RADEON_SIGNED_RGB_SHIFT 30
-# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
+# define RADEON_SIGNED_ALPHA_MASK (1U << 31)
# define RADEON_SIGNED_ALPHA_SHIFT 31
#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
@@ -2558,7 +2558,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TCL_VTX_Z1 (1 << 28)
# define RADEON_TCL_VTX_W1 (1 << 29)
# define RADEON_TCL_VTX_NORM1 (1 << 30)
-# define RADEON_TCL_VTX_Z0 (1 << 31)
+# define RADEON_TCL_VTX_Z0 (1U << 31)
#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
@@ -2667,7 +2667,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
# define RADEON_CULL_FRONT (1 << 29)
# define RADEON_CULL_BACK (1 << 30)
-# define RADEON_FORCE_W_TO_ONE (1 << 31)
+# define RADEON_FORCE_W_TO_ONE (1U << 31)
#define RADEON_SE_VPORT_XSCALE 0x1d98
#define RADEON_SE_VPORT_XOFFSET 0x1d9c
@@ -3306,7 +3306,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_MAX_FETCH_SHIFT 18
# define RADEON_MAX_FETCH_MASK (0x3 << 18)
# define RADEON_RB_NO_UPDATE (1 << 27)
-# define RADEON_RB_RPTR_WR_ENA (1 << 31)
+# define RADEON_RB_RPTR_WR_ENA (1U << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@@ -3320,7 +3320,7 @@ __FBSDID("$FreeBSD$");
# define R600_RB_BUFSZ(x) ((x) << 0)
# define R600_RB_BLKSZ(x) ((x) << 8)
# define R600_RB_NO_UPDATE (1 << 27)
-# define R600_RB_RPTR_WR_ENA (1 << 31)
+# define R600_RB_RPTR_WR_ENA (1U << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
@@ -3519,7 +3519,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TV_FIFO_CE_EN (1 << 10)
# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
-# define RADEON_TV_ON (1 << 31)
+# define RADEON_TV_ON (1U << 31)
#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
# define RADEON_Y_RED_EN (1 << 0)
# define RADEON_C_GRN_EN (1 << 1)
@@ -3651,7 +3651,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TVPVG_MASK (7 << 11)
# define RADEON_TVPDC_SHIFT 14
# define RADEON_TVPDC_MASK (3 << 14)
-# define RADEON_TVPLL_TEST_DIS (1 << 31)
+# define RADEON_TVPLL_TEST_DIS (1U << 31)
# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
#define RS400_DISP2_REQ_CNTL1 0xe30
diff --git a/sys/dev/drm2/radeon/rv770d.h b/sys/dev/drm2/radeon/rv770d.h
index 1f2c23c554ff..e281444f833c 100644
--- a/sys/dev/drm2/radeon/rv770d.h
+++ b/sys/dev/drm2/radeon/rv770d.h
@@ -82,7 +82,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
@@ -312,7 +312,7 @@ __FBSDID("$FreeBSD$");
#define SYNC_WALKER (1 << 25)
#define SYNC_ALIGNER (1 << 26)
#define BILINEAR_PRECISION_6_BIT (0 << 31)
-#define BILINEAR_PRECISION_8_BIT (1 << 31)
+#define BILINEAR_PRECISION_8_BIT (1U << 31)
#define TCP_CNTL 0x9610
#define TCP_CHAN_STEER 0x9614
@@ -537,7 +537,7 @@ __FBSDID("$FreeBSD$");
# define AFMT_AUDIO_CRC_EN (1 << 0)
#define AFMT_RAMP_CONTROL0 0x74e0
# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
-# define AFMT_RAMP_DATA_SIGN (1 << 31)
+# define AFMT_RAMP_DATA_SIGN (1U << 31)
#define AFMT_RAMP_CONTROL1 0x74e4
# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
@@ -622,7 +622,7 @@ __FBSDID("$FreeBSD$");
# define PIN1_AUDIO_ENABLED (1 << 25)
# define PIN2_AUDIO_ENABLED (1 << 26)
# define PIN3_AUDIO_ENABLED (1 << 27)
-# define AUDIO_ENABLED (1 << 31)
+# define AUDIO_ENABLED (1U << 31)
#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
diff --git a/sys/dev/drm2/radeon/sid.h b/sys/dev/drm2/radeon/sid.h
index 028916f17ebd..7aa21c1442ac 100644
--- a/sys/dev/drm2/radeon/sid.h
+++ b/sys/dev/drm2/radeon/sid.h
@@ -199,7 +199,7 @@ __FBSDID("$FreeBSD$");
#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
#define TRAIN_DONE_D0 (1 << 30)
-#define TRAIN_DONE_D1 (1 << 31)
+#define TRAIN_DONE_D1 (1U << 31)
#define MC_SEQ_SUP_CNTL 0x28c8
#define RUN_MASK (1 << 0)
@@ -227,7 +227,7 @@ __FBSDID("$FreeBSD$");
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
-# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
+# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@@ -414,7 +414,7 @@ __FBSDID("$FreeBSD$");
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
-#define GUI_ACTIVE (1 << 31)
+#define GUI_ACTIVE (1U << 31)
#define GRBM_STATUS_SE0 0x8014
#define GRBM_STATUS_SE1 0x8018
#define SE_DB_CLEAN (1 << 1)
@@ -427,7 +427,7 @@ __FBSDID("$FreeBSD$");
#define SE_SPI_BUSY (1 << 27)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
-#define SE_CB_BUSY (1 << 31)
+#define SE_CB_BUSY (1U << 31)
#define GRBM_SOFT_RESET 0x8020
#define SOFT_RESET_CP (1 << 0)
@@ -451,7 +451,7 @@ __FBSDID("$FreeBSD$");
#define SE_INDEX(x) ((x) << 16)
#define SH_BROADCAST_WRITES (1 << 29)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
-#define SE_BROADCAST_WRITES (1 << 31)
+#define SE_BROADCAST_WRITES (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@@ -672,7 +672,7 @@ __FBSDID("$FreeBSD$");
#define RB_BLKSZ(x) ((x) << 8)
#define BUF_SWAP_32BIT (2 << 16)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define CP_RB0_RPTR_ADDR 0xC10C
#define CP_RB0_RPTR_ADDR_HI 0xC110
@@ -706,7 +706,7 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_ENABLE (1 << 26)
# define CP_RINGID2_INT_ENABLE (1 << 29)
# define CP_RINGID1_INT_ENABLE (1 << 30)
-# define CP_RINGID0_INT_ENABLE (1 << 31)
+# define CP_RINGID0_INT_ENABLE (1U << 31)
#define CP_INT_STATUS_RING0 0xC1B4
#define CP_INT_STATUS_RING1 0xC1B8
#define CP_INT_STATUS_RING2 0xC1BC
@@ -714,7 +714,7 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_STAT (1 << 26)
# define CP_RINGID2_INT_STAT (1 << 29)
# define CP_RINGID1_INT_STAT (1 << 30)
-# define CP_RINGID0_INT_STAT (1 << 31)
+# define CP_RINGID0_INT_STAT (1U << 31)
#define CP_DEBUG 0xC1FC
@@ -890,7 +890,7 @@ __FBSDID("$FreeBSD$");
* 1 - GDS
* 2 - DATA
*/
-# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
+# define PACKET3_CP_DMA_CP_SYNC (1U << 31)
/* COMMAND */
# define PACKET3_CP_DMA_DIS_WC (1 << 21)
# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
diff --git a/sys/dev/drm2/ttm/ttm_bo.c b/sys/dev/drm2/ttm/ttm_bo.c
index 3b135404ed6f..c1c4fbf57e17 100644
--- a/sys/dev/drm2/ttm/ttm_bo.c
+++ b/sys/dev/drm2/ttm/ttm_bo.c
@@ -216,7 +216,7 @@ int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo,
* Already reserved by a thread that will not back
* off for us. We need to back off.
*/
- if (unlikely(sequence - bo->val_seq < (1 << 31)))
+ if (unlikely(sequence - bo->val_seq < (1U << 31)))
return -EAGAIN;
}
@@ -235,7 +235,7 @@ int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo,
* Wake up waiters that may need to recheck for deadlock,
* if we decreased the sequence number.
*/
- if (unlikely((bo->val_seq - sequence < (1 << 31))
+ if (unlikely((bo->val_seq - sequence < (1U << 31))
|| !bo->seq_valid))
wake_up = true;
@@ -313,7 +313,7 @@ int ttm_bo_reserve_slowpath_nolru(struct ttm_buffer_object *bo,
return ret;
}
- if ((bo->val_seq - sequence < (1 << 31)) || !bo->seq_valid)
+ if ((bo->val_seq - sequence < (1U << 31)) || !bo->seq_valid)
wake_up = true;
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-23 06:25:29 +0000