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| author | Pyun YongHyeon <yongari@FreeBSD.org> | 2010-10-04 18:09:01 +0000 |
|---|---|---|
| committer | Pyun YongHyeon <yongari@FreeBSD.org> | 2010-10-04 18:09:01 +0000 |
| commit | d255f2a9dfe233de5b1e166a1b014250568c0821 (patch) | |
| tree | 53f5c29903cb644c7fafe594ae02c197f6c5c1c3 /sys/dev/bge | |
| parent | 1cd4773b5da2b8f6cf0d7bd32237167dd4fff28d (diff) | |
| download | src-d255f2a9dfe233de5b1e166a1b014250568c0821.tar.gz src-d255f2a9dfe233de5b1e166a1b014250568c0821.zip | |
Enable fix for read DMA FIFO overruns on controllers that have this
fix. Note, we still need workaround for controllers that lacks this
fix and it needs more work in RX BD updating.
Submitted by: davidch
Notes
Notes:
svn path=/head/; revision=213411
Diffstat (limited to 'sys/dev/bge')
| -rw-r--r-- | sys/dev/bge/if_bge.c | 13 | ||||
| -rw-r--r-- | sys/dev/bge/if_bgereg.h | 4 |
2 files changed, 17 insertions, 0 deletions
diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c index 720846f09bad..317bcd25869e 100644 --- a/sys/dev/bge/if_bge.c +++ b/sys/dev/bge/if_bge.c @@ -1858,6 +1858,19 @@ bge_blockinit(struct bge_softc *sc) sc->bge_asicrev == BGE_ASICREV_BCM57780) val |= BGE_RDMAMODE_TSO6_ENABLE; } + if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || + sc->bge_asicrev == BGE_ASICREV_BCM5784 || + sc->bge_asicrev == BGE_ASICREV_BCM5785 || + sc->bge_asicrev == BGE_ASICREV_BCM57780) { + /* + * Enable fix for read DMA FIFO overruns. + * The fix is to limit the number of RX BDs + * the hardware would fetch at a fime. + */ + CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, + CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) | + BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); + } CSR_WRITE_4(sc, BGE_RDMA_MODE, val); DELAY(40); diff --git a/sys/dev/bge/if_bgereg.h b/sys/dev/bge/if_bgereg.h index 1f16e69d153b..87abca8f2769 100644 --- a/sys/dev/bge/if_bgereg.h +++ b/sys/dev/bge/if_bgereg.h @@ -1431,6 +1431,7 @@ */ #define BGE_RDMA_MODE 0x4800 #define BGE_RDMA_STATUS 0x4804 +#define BGE_RDMA_RSRVCTRL 0x4900 /* Read DMA mode register */ #define BGE_RDMAMODE_RESET 0x00000001 @@ -1462,6 +1463,9 @@ #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 +/* Read DMA Reserved Control register */ +#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 + /* * Write DMA control registers */ |