diff options
author | Juli Mallett <jmallett@FreeBSD.org> | 2010-12-16 07:20:38 +0000 |
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committer | Juli Mallett <jmallett@FreeBSD.org> | 2010-12-16 07:20:38 +0000 |
commit | 4a7b75273b789b77cfedbe7b4b9c2ba2c4acc6ed (patch) | |
tree | f0c81ec1d581929e9183f2375a74ccdd3a385151 /sys/contrib | |
parent | 3693ce57327eaa1971498a9e5e49fa448cc9ae87 (diff) | |
download | src-4a7b75273b789b77cfedbe7b4b9c2ba2c4acc6ed.tar.gz src-4a7b75273b789b77cfedbe7b4b9c2ba2c4acc6ed.zip |
o) Add support for the Lanner MR-321X/MR-325, which is just a modified MR-320.
o) On the Lanner MR-730, disable PCIe lane swap, per vendor.
Notes
Notes:
svn path=/head/; revision=216476
Diffstat (limited to 'sys/contrib')
-rw-r--r-- | sys/contrib/octeon-sdk/cvmx-app-init.h | 2 | ||||
-rw-r--r-- | sys/contrib/octeon-sdk/cvmx-helper-board.c | 3 | ||||
-rw-r--r-- | sys/contrib/octeon-sdk/cvmx-helper-rgmii.c | 1 | ||||
-rw-r--r-- | sys/contrib/octeon-sdk/cvmx-pcie.c | 11 |
4 files changed, 16 insertions, 1 deletions
diff --git a/sys/contrib/octeon-sdk/cvmx-app-init.h b/sys/contrib/octeon-sdk/cvmx-app-init.h index 1138e2cd6bf3..2912cfd412db 100644 --- a/sys/contrib/octeon-sdk/cvmx-app-init.h +++ b/sys/contrib/octeon-sdk/cvmx-app-init.h @@ -223,6 +223,7 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, #if defined(OCTEON_VENDOR_LANNER) CVMX_BOARD_TYPE_CUST_LANNER_MR320= 20002, + CVMX_BOARD_TYPE_CUST_LANNER_MR321X=20007, #endif CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, @@ -336,6 +337,7 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) #if defined(OCTEON_VENDOR_LANNER) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR320) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR321X) #endif ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) diff --git a/sys/contrib/octeon-sdk/cvmx-helper-board.c b/sys/contrib/octeon-sdk/cvmx-helper-board.c index bbac3e755a7d..49311678df0f 100644 --- a/sys/contrib/octeon-sdk/cvmx-helper-board.c +++ b/sys/contrib/octeon-sdk/cvmx-helper-board.c @@ -276,6 +276,7 @@ int cvmx_helper_board_get_mii_address(int ipd_port) return ipd_port; return -1; case CVMX_BOARD_TYPE_CUST_LANNER_MR320: + case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: /* Port 0 is a Marvell 88E6161 switch, ports 1 and 2 are Marvell 88E1111 interfaces. */ switch (ipd_port) { @@ -417,6 +418,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) is_broadcom_phy = 1; break; case CVMX_BOARD_TYPE_CUST_LANNER_MR320: + case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: /* Port 0 connects to the switch */ if (ipd_port == 0) { @@ -860,6 +862,7 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void) case CVMX_BOARD_TYPE_LANAI2_G: #if defined(OCTEON_VENDOR_LANNER) case CVMX_BOARD_TYPE_CUST_LANNER_MR320: + case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: #endif return USB_CLOCK_TYPE_CRYSTAL_12; } diff --git a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c index e62c46f0d7c5..9cecb6ae2acf 100644 --- a/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c +++ b/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c @@ -239,6 +239,7 @@ int __cvmx_helper_rgmii_enable(int interface) #if defined(OCTEON_VENDOR_LANNER) switch (cvmx_sysinfo_get()->board_type) { case CVMX_BOARD_TYPE_CUST_LANNER_MR320: + case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: if (port == 0) { cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 4); } else { diff --git a/sys/contrib/octeon-sdk/cvmx-pcie.c b/sys/contrib/octeon-sdk/cvmx-pcie.c index 8053737e9737..7c8dc2a39843 100644 --- a/sys/contrib/octeon-sdk/cvmx-pcie.c +++ b/sys/contrib/octeon-sdk/cvmx-pcie.c @@ -392,7 +392,16 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port) /* Lane swap needs to be manually enabled for CN52XX */ if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) { - pescx_ctl_status.s.lane_swp = 1; + switch (cvmx_sysinfo_get()->board_type) + { +#if defined(OCTEON_VENDOR_LANNER) + case CVMX_BOARD_TYPE_CUST_LANNER_MR730: + break; +#endif + default: + pescx_ctl_status.s.lane_swp = 1; + break; + } cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),pescx_ctl_status.u64); } |