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| author | KATO Takenori <kato@FreeBSD.org> | 2000-06-13 09:10:37 +0000 |
|---|---|---|
| committer | KATO Takenori <kato@FreeBSD.org> | 2000-06-13 09:10:37 +0000 |
| commit | 65cbb03cfe6a3d0fd909cde57aa679398cf4a615 (patch) | |
| tree | d9be66d03fe16790bf7e54e42f5990540b4e2593 /sys/conf/options.pc98 | |
| parent | ac377c3e15692f549c44211128d524759ae8f514 (diff) | |
| download | src-65cbb03cfe6a3d0fd909cde57aa679398cf4a615.tar.gz src-65cbb03cfe6a3d0fd909cde57aa679398cf4a615.zip | |
Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support
Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is
defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is
enabled through MSR 0x11e. The L2 cache latency value can be
specified by CPU_L2_LATENCY option. Default value of L2 cache latency
is 5.
These options are useful if you use Socket 8 to Socket 370 converter
(e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2
cache of Mendocino Celeron CPUs because they don't know Celeron CPUs.
These options are needles if you use a Coppermine (FCPGA) Celeron or
PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache
is always enabled.
Notes
Notes:
svn path=/head/; revision=61616
Diffstat (limited to 'sys/conf/options.pc98')
| -rw-r--r-- | sys/conf/options.pc98 | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/conf/options.pc98 b/sys/conf/options.pc98 index ce089637e745..570a73ef8f27 100644 --- a/sys/conf/options.pc98 +++ b/sys/conf/options.pc98 @@ -50,7 +50,9 @@ CPU_DISABLE_5X86_LSSER opt_cpu.h CPU_FASTER_5X86_FPU opt_cpu.h CPU_I486_ON_386 opt_cpu.h CPU_IORT opt_cpu.h +CPU_L2_LATENCY opt_cpu.h CPU_LOOP_EN opt_cpu.h +CPU_PPRO2CELERON opt_cpu.h CPU_RSTK_EN opt_cpu.h CPU_SUSP_HLT opt_cpu.h CPU_UPGRADE_HW_CACHE opt_cpu.h |