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| author | Ruslan Bukin <br@FreeBSD.org> | 2016-09-01 14:58:11 +0000 |
|---|---|---|
| committer | Ruslan Bukin <br@FreeBSD.org> | 2016-09-01 14:58:11 +0000 |
| commit | 9862cef0409368e9bcba5a44f8ba2ad6a2e1a4b5 (patch) | |
| tree | ab7d7eaab64d2db0b70d8c7793b1c20ed8e51b1b /sys/boot | |
| parent | e12a269749e89d4f9af4d7e96465cc4cf1d7a234 (diff) | |
| download | src-9862cef0409368e9bcba5a44f8ba2ad6a2e1a4b5.tar.gz src-9862cef0409368e9bcba5a44f8ba2ad6a2e1a4b5.zip | |
o Separate rtc and timecmp registers: they are different across
RISC-V cpu implementations.
o Update RocketChip device tree source (DTS).
We now support latest verison of RocketChip synthesized on
Xilinx FPGA (Zedboard).
RocketChip is an implementation of RISC-V processor written on
Chisel hardware construction language.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Notes
Notes:
svn path=/head/; revision=305208
Diffstat (limited to 'sys/boot')
| -rw-r--r-- | sys/boot/fdt/dts/riscv/rocket.dts | 24 | ||||
| -rw-r--r-- | sys/boot/fdt/dts/riscv/spike.dts | 7 |
2 files changed, 19 insertions, 12 deletions
diff --git a/sys/boot/fdt/dts/riscv/rocket.dts b/sys/boot/fdt/dts/riscv/rocket.dts index 8ce718d8295f..691f41209cf0 100644 --- a/sys/boot/fdt/dts/riscv/rocket.dts +++ b/sys/boot/fdt/dts/riscv/rocket.dts @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com> + * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -37,8 +37,8 @@ /dts-v1/; / { - model = "UC Berkeley Spike Simulator RV64I"; - compatible = "riscv,rv64i"; + model = "RocketChip RV64"; + compatible = "riscv,rv64"; #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <1>; @@ -49,8 +49,8 @@ cpu@0 { device_type = "cpu"; - compatible = "riscv,rv64i"; - reg = <0x40002000>; + compatible = "riscv,rv64"; + reg = <0x0>; }; }; @@ -59,13 +59,17 @@ }; memory { + /* + * This is not used currently. + * We take information from sbi_query_memory. + */ device_type = "memory"; - reg = <0x0 0x10000000>; /* 256MB at 0x0 */ + reg = <0x80000000 0x10000000>; /* 256MB at 0x80000000 */ }; soc { - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; #interrupt-cells = <1>; compatible = "simple-bus"; @@ -78,7 +82,9 @@ timer0: timer@0 { compatible = "riscv,timer"; - interrupts = < 1 >; + reg = < 0x4400bff8 0x0008 >, /* rtc */ + < 0x44004000 0x1000 >; /* timecmp */ + interrupts = < 5 >; interrupt-parent = < &pic0 >; clock-frequency = < 1000000 >; }; diff --git a/sys/boot/fdt/dts/riscv/spike.dts b/sys/boot/fdt/dts/riscv/spike.dts index dfe27f349351..30ce7f5e13dc 100644 --- a/sys/boot/fdt/dts/riscv/spike.dts +++ b/sys/boot/fdt/dts/riscv/spike.dts @@ -50,13 +50,13 @@ cpu@0 { device_type = "cpu"; compatible = "riscv,rv64"; - reg = <0x40001000>; + reg = <0x0>; }; cpu@1 { device_type = "cpu"; compatible = "riscv,rv64"; - reg = <0x40002000>; + reg = <0x0>; }; }; @@ -88,7 +88,8 @@ timer0: timer@0 { compatible = "riscv,timer"; - reg = < 0x40000000 0x100 >; + reg = < 0x40000000 0x0008 >, /* rtc */ + < 0x40000008 0x1000 >; /* timecmp */ interrupts = < 5 >; interrupt-parent = < &pic0 >; clock-frequency = < 1000000 >; |