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| author | Olivier Houchard <cognet@FreeBSD.org> | 2007-11-28 22:21:17 +0000 |
|---|---|---|
| committer | Olivier Houchard <cognet@FreeBSD.org> | 2007-11-28 22:21:17 +0000 |
| commit | 85d18774deeeca9d9d9ac21207b278f1c3d514fb (patch) | |
| tree | 21fea872c4f598505b507813d3c0594b6ec6d0f3 /sys/arm | |
| parent | 98bbce55fa1469293d57ebb30812748b949762f6 (diff) | |
| download | src-85d18774deeeca9d9d9ac21207b278f1c3d514fb.tar.gz src-85d18774deeeca9d9d9ac21207b278f1c3d514fb.zip | |
Correct the logic : we can just invalidate the cache lines, and not
write-back them, only if PREWRITE is not set, and if the buffer is
cache-line aligned.
MFC After: 1 week
Notes
Notes:
svn path=/head/; revision=174051
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/arm/busdma_machdep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/arm/arm/busdma_machdep.c b/sys/arm/arm/busdma_machdep.c index 6c8195ba8284..61c1ea22e240 100644 --- a/sys/arm/arm/busdma_machdep.c +++ b/sys/arm/arm/busdma_machdep.c @@ -1090,7 +1090,7 @@ bus_dmamap_sync_buf(void *buf, int len, bus_dmasync_op_t op) cpu_l2cache_wb_range((vm_offset_t)buf, len); } if (op & BUS_DMASYNC_PREREAD) { - if ((op & BUS_DMASYNC_PREWRITE) || + if (!(op & BUS_DMASYNC_PREWRITE) && ((((vm_offset_t)(buf) | len) & arm_dcache_align_mask) == 0)) { cpu_dcache_inv_range((vm_offset_t)buf, len); cpu_l2cache_inv_range((vm_offset_t)buf, len); |