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| author | Andrew Turner <andrew@FreeBSD.org> | 2024-08-19 12:43:05 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2024-08-20 08:49:15 +0000 |
| commit | 4db15ab2c65e60f4d49d40ad6922ca301b184510 (patch) | |
| tree | 18612ec3753a160074d1ef87d2f7fe97547660a5 /sys/arm64/include | |
| parent | 43e8849bc29414036ccaef7788de95a07ad32ab5 (diff) | |
| download | src-4db15ab2c65e60f4d49d40ad6922ca301b184510.tar.gz src-4db15ab2c65e60f4d49d40ad6922ca301b184510.zip | |
arm64: Add counter timer registers to armreg.h
Reviewed by: imp
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46071
Diffstat (limited to 'sys/arm64/include')
| -rw-r--r-- | sys/arm64/include/armreg.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index b2ab472dad0d..ce21bf4de0a9 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -231,6 +231,22 @@ #define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ #define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ +/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ +#define CNTKCTL_EL1 MRS_REG(CNTKCTL_EL0) +#define CNTKCTL_EL1_op0 3 +#define CNTKCTL_EL1_op1 0 +#define CNTKCTL_EL1_CRn 14 +#define CNTKCTL_EL1_CRm 1 +#define CNTKCTL_EL1_op2 0 + +/* CNTKCTL_EL12 - Counter-timer Kernel Control Register */ +#define CNTKCTL_EL12 MRS_REG(CNTKCTL_EL0) +#define CNTKCTL_EL12_op0 3 +#define CNTKCTL_EL12_op1 5 +#define CNTKCTL_EL12_CRn 14 +#define CNTKCTL_EL12_CRm 1 +#define CNTKCTL_EL12_op2 0 + /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ #define CNTP_CTL_EL0 MRS_REG(CNTP_CTL_EL0) #define CNTP_CTL_EL0_op0 3 @@ -266,6 +282,38 @@ #define CNTPCT_EL0_CRm 0 #define CNTPCT_EL0_op2 1 +/* CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register */ +#define CNTV_CTL_EL0 MRS_REG(CNTV_CTL_EL0) +#define CNTV_CTL_EL0_op0 3 +#define CNTV_CTL_EL0_op1 3 +#define CNTV_CTL_EL0_CRn 14 +#define CNTV_CTL_EL0_CRm 3 +#define CNTV_CTL_EL0_op2 1 + +/* CNTV_CTL_EL02 - Counter-timer Virtual Timer Control register */ +#define CNTV_CTL_EL02 MRS_REG(CNTV_CTL_EL02) +#define CNTV_CTL_EL02_op0 3 +#define CNTV_CTL_EL02_op1 5 +#define CNTV_CTL_EL02_CRn 14 +#define CNTV_CTL_EL02_CRm 3 +#define CNTV_CTL_EL02_op2 1 + +/* CNTV_CVAL_EL0 - Counter-timer Virtual Timer CompareValue register */ +#define CNTV_CVAL_EL0 MRS_REG(CNTV_CVAL_EL0) +#define CNTV_CVAL_EL0_op0 3 +#define CNTV_CVAL_EL0_op1 3 +#define CNTV_CVAL_EL0_CRn 14 +#define CNTV_CVAL_EL0_CRm 3 +#define CNTV_CVAL_EL0_op2 2 + +/* CNTV_CVAL_EL02 - Counter-timer Virtual Timer CompareValue register */ +#define CNTV_CVAL_EL02 MRS_REG(CNTV_CVAL_EL02) +#define CNTV_CVAL_EL02_op0 3 +#define CNTV_CVAL_EL02_op1 5 +#define CNTV_CVAL_EL02_CRn 14 +#define CNTV_CVAL_EL02_CRm 3 +#define CNTV_CVAL_EL02_op2 2 + /* CONTEXTIDR_EL1 - Context ID register */ #define CONTEXTIDR_EL1 MRS_REG(CONTEXTIDR_EL1) #define CONTEXTIDR_EL1_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL1) |