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| author | Konstantin Belousov <kib@FreeBSD.org> | 2015-06-06 22:03:24 +0000 |
|---|---|---|
| committer | Konstantin Belousov <kib@FreeBSD.org> | 2015-06-06 22:03:24 +0000 |
| commit | 32a1e9e4a51c8fb2d3b63d72fb9398617157b059 (patch) | |
| tree | 398da1ac17e54eb86b155ad057cd1b47445c56cb /sys/amd64 | |
| parent | 284743a8673543164efe9015ee85e4723b5daaca (diff) | |
| download | src-32a1e9e4a51c8fb2d3b63d72fb9398617157b059.tar.gz src-32a1e9e4a51c8fb2d3b63d72fb9398617157b059.zip | |
Update print_INTEL_TLB() by the tag values from the Intel SDM
rev. 55. The modern CPUs cache and TLB descriptions looked quite
questionable without the update, e.g. Haswell i7 4770S reported:
Data TLB: 4 KB pages, 4-way set associative, 64 entries
L2 cache: 256 kbytes, 8-way associative, 64 bytes/line
After the update, the report is:
Data TLB: 1 GByte pages, 4-way set associative, 4 entries
Data TLB: 4 KB pages, 4-way set associative, 64 entries
Instruction TLB: 2M/4M pages, fully associative, 8 entries
Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
64-Byte prefetching
Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
L2 cache: 256 kbytes, 8-way associative, 64 bytes/line
Some tags were apparently removed from the table 3-21, Vol. 2A. Keep
them around, but add a comment stating the removal.
Update the format line for cpu_stdext_feature according to the bits
from the SDM rev.55. It appears that Haswells do not store %cs and
%ds values in the FPU save area.
Store content of the %ecx register from the CPUID leaf 0x7
subleaf 0 as cpu_stdext_feature2 and print defined bits from it,
again acording to SDM rev. 55.
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Notes
Notes:
svn path=/head/; revision=284104
Diffstat (limited to 'sys/amd64')
| -rw-r--r-- | sys/amd64/amd64/initcpu.c | 1 | ||||
| -rw-r--r-- | sys/amd64/include/md_var.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 8551d27906c3..36f2d0f027b2 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -74,6 +74,7 @@ u_int cpu_fxsr; /* SSE enabled */ u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ u_int cpu_clflush_line_size = 32; u_int cpu_stdext_feature; +u_int cpu_stdext_feature2; u_int cpu_max_ext_state_size; u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ diff --git a/sys/amd64/include/md_var.h b/sys/amd64/include/md_var.h index 0813e5fb74d3..954df3ec9c06 100644 --- a/sys/amd64/include/md_var.h +++ b/sys/amd64/include/md_var.h @@ -49,6 +49,7 @@ extern u_int via_feature_rng; extern u_int via_feature_xcrypt; extern u_int cpu_clflush_line_size; extern u_int cpu_stdext_feature; +extern u_int cpu_stdext_feature2; extern u_int cpu_fxsr; extern u_int cpu_high; extern u_int cpu_id; |