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author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/Target/X86/X86Subtarget.h | |
parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
download | src-cfca06d7963fa0909f90483b42a6d7d194d01e08.tar.gz src-cfca06d7963fa0909f90483b42a6d7d194d01e08.zip |
Vendor import of llvm-project master 2e10b7a39b9, the last commit beforevendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9vendor/llvm-project/master
the llvmorg-12-init tag, from which release/11.x was branched.
Notes
Notes:
svn path=/vendor/llvm-project/master/; revision=363578
svn path=/vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9/; revision=363579; tag=vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
-rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.h | 76 |
1 files changed, 66 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index f4e8d30328ca..de45d357e3c2 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -17,15 +17,9 @@ #include "X86ISelLowering.h" #include "X86InstrInfo.h" #include "X86SelectionDAGInfo.h" -#include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" -#include "llvm/CodeGen/GlobalISel/CallLowering.h" -#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" -#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/CallingConv.h" -#include "llvm/Target/TargetMachine.h" #include <climits> #include <memory> @@ -34,7 +28,13 @@ namespace llvm { +class CallLowering; class GlobalValue; +class InstructionSelector; +class LegalizerInfo; +class RegisterBankInfo; +class StringRef; +class TargetMachine; /// The X86 backend supports a number of different styles of PIC. /// @@ -258,6 +258,10 @@ protected: bool InsertVZEROUPPER = false; /// True if there is no performance penalty for writing NOPs with up to + /// 7 bytes. + bool HasFast7ByteNOP = false; + + /// True if there is no performance penalty for writing NOPs with up to /// 11 bytes. bool HasFast11ByteNOP = false; @@ -393,6 +397,17 @@ protected: /// Processor supports PCONFIG instruction bool HasPCONFIG = false; + /// Processor supports SERIALIZE instruction + bool HasSERIALIZE = false; + + /// Processor supports TSXLDTRK instruction + bool HasTSXLDTRK = false; + + /// Processor has AMX support + bool HasAMXTILE = false; + bool HasAMXBF16 = false; + bool HasAMXINT8 = false; + /// Processor has a single uop BEXTR implementation. bool HasFastBEXTR = false; @@ -421,6 +436,19 @@ protected: /// than emitting one inside the compiler. bool UseRetpolineExternalThunk = false; + /// Prevent generation of indirect call/branch instructions from memory, + /// and force all indirect call/branch instructions from a register to be + /// preceded by an LFENCE. Also decompose RET instructions into a + /// POP+LFENCE+JMP sequence. + bool UseLVIControlFlowIntegrity = false; + + /// Enable Speculative Execution Side Effect Suppression + bool UseSpeculativeExecutionSideEffectSuppression = false; + + /// Insert LFENCE instructions to prevent data speculatively injected into + /// loads from being used maliciously. + bool UseLVILoadHardening = false; + /// Use software floating point for code generation. bool UseSoftFloat = false; @@ -627,8 +655,15 @@ public: bool hasRTM() const { return HasRTM; } bool hasADX() const { return HasADX; } bool hasSHA() const { return HasSHA; } - bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; } + bool hasPRFCHW() const { return HasPRFCHW; } bool hasPREFETCHWT1() const { return HasPREFETCHWT1; } + bool hasPrefetchW() const { + // The PREFETCHW instruction was added with 3DNow but later CPUs gave it + // its own CPUID bit as part of deprecating 3DNow. Intel eventually added + // it and KNL has another that prefetches to L2 cache. We assume the + // L1 version exists if the L2 version does. + return has3DNow() || hasPRFCHW() || hasPREFETCHWT1(); + } bool hasSSEPrefetch() const { // We implicitly enable these when we have a write prefix supporting cache // level OR if we have prfchw, but don't already have a read prefetch from @@ -702,13 +737,34 @@ public: bool threewayBranchProfitable() const { return ThreewayBranchProfitable; } bool hasINVPCID() const { return HasINVPCID; } bool hasENQCMD() const { return HasENQCMD; } + bool hasSERIALIZE() const { return HasSERIALIZE; } + bool hasTSXLDTRK() const { return HasTSXLDTRK; } bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; } bool useRetpolineIndirectBranches() const { return UseRetpolineIndirectBranches; } + bool hasAMXTILE() const { return HasAMXTILE; } + bool hasAMXBF16() const { return HasAMXBF16; } + bool hasAMXINT8() const { return HasAMXINT8; } bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } + + // These are generic getters that OR together all of the thunk types + // supported by the subtarget. Therefore useIndirectThunk*() will return true + // if any respective thunk feature is enabled. + bool useIndirectThunkCalls() const { + return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity(); + } + bool useIndirectThunkBranches() const { + return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity(); + } + bool preferMaskRegisters() const { return PreferMaskRegisters; } bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; } + bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; } + bool useLVILoadHardening() const { return UseLVILoadHardening; } + bool useSpeculativeExecutionSideEffectSuppression() const { + return UseSpeculativeExecutionSideEffectSuppression; + } unsigned getPreferVectorWidth() const { return PreferVectorWidth; } unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } @@ -806,7 +862,7 @@ public: return PICStyle == PICStyles::Style::StubPIC; } - bool isPositionIndependent() const { return TM.isPositionIndependent(); } + bool isPositionIndependent() const; bool isCallingConvWin64(CallingConv::ID CC) const { switch (CC) { @@ -853,10 +909,10 @@ public: /// Return true if the subtarget allows calls to immediate address. bool isLegalToCallImmediateAddr() const; - /// If we are using retpolines, we need to expand indirectbr to avoid it + /// If we are using indirect thunks, we need to expand indirectbr to avoid it /// lowering to an actual indirect jump. bool enableIndirectBrExpand() const override { - return useRetpolineIndirectBranches(); + return useIndirectThunkBranches(); } /// Enable the MachineScheduler pass for all X86 subtargets. |