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| author | Dimitry Andric <dim@FreeBSD.org> | 2021-07-29 20:15:26 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-07-29 20:15:26 +0000 |
| commit | 344a3780b2e33f6ca763666c380202b18aab72a3 (patch) | |
| tree | f0b203ee6eb71d7fdd792373e3c81eb18d6934dd /llvm/lib/Target/X86/X86ScheduleZnver1.td | |
| parent | b60736ec1405bb0a8dd40989f67ef4c93da068ab (diff) | |
| download | src-344a3780b2e33f6ca763666c380202b18aab72a3.tar.gz src-344a3780b2e33f6ca763666c380202b18aab72a3.zip | |
Vendor import of llvm-project main 88e66fa60ae5, the last commit beforevendor/llvm-project/llvmorg-13-init-16847-g88e66fa60ae5vendor/llvm-project/llvmorg-12.0.1-rc2-0-ge7dac564cd0evendor/llvm-project/llvmorg-12.0.1-0-gfed41342a82f
the upstream release/13.x branch was created.
Diffstat (limited to 'llvm/lib/Target/X86/X86ScheduleZnver1.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index fe09d6f85221..12f8e7cc76f7 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -179,6 +179,10 @@ def : WriteRes<WriteStoreNT, [ZnAGU]>; def : WriteRes<WriteMove, [ZnALU]>; def : WriteRes<WriteLoad, [ZnAGU]> { let Latency = 8; } +// Model the effect of clobbering the read-write mask operand of the GATHER operation. +// Does not cost anything by itself, only has latency, matching that of the WriteLoad, +def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 8; let NumMicroOps = 0; } + def : WriteRes<WriteZero, []>; def : WriteRes<WriteLEA, [ZnALU]>; defm : ZnWriteResPair<WriteALU, [ZnALU], 1>; @@ -437,6 +441,7 @@ defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>; defm : ZnWriteResFpuPair<WriteBlendY, [ZnFPU01], 1>; defm : X86WriteResPairUnsupported<WriteBlendZ>; defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>; +defm : ZnWriteResFpuPair<WriteVPMOV256, [ZnFPU12], 1, [1], 2>; defm : ZnWriteResFpuPair<WriteVarShuffle256, [ZnFPU], 2>; defm : ZnWriteResFpuPair<WritePSADBW, [ZnFPU0], 3>; defm : ZnWriteResFpuPair<WritePSADBWX, [ZnFPU0], 3>; @@ -969,7 +974,7 @@ def : InstRW<[ZnWriteFPU03], (instregex "FICOM(P?)(16|32)m")>; def : InstRW<[ZnWriteFPU0Lat1], (instregex "TST_F")>; // FXAM. -def : InstRW<[ZnWriteFPU3Lat1], (instrs FXAM)>; +def : InstRW<[ZnWriteFPU3Lat1], (instrs XAM_F)>; // FPREM. def : InstRW<[WriteMicrocoded], (instrs FPREM)>; @@ -1019,11 +1024,6 @@ def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWirm, MMX_PACKSSWBirm, MMX_PACKUSWBirm)>; -// VPMOVSX/ZX BW BD BQ WD WQ DQ. -// y <- x. -def : InstRW<[ZnWriteFPU12Y], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrr")>; -def : InstRW<[ZnWriteFPU12Ym], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrm")>; - def ZnWriteFPU013 : SchedWriteRes<[ZnFPU013]> ; def ZnWriteFPU013Y : SchedWriteRes<[ZnFPU013]> { let Latency = 2; |