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| author | Dimitry Andric <dim@FreeBSD.org> | 2021-12-25 22:30:44 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-12-25 22:30:44 +0000 |
| commit | 77fc4c146f0870ffb09c1afb823ccbe742c5e6ff (patch) | |
| tree | 5c0eb39553003b9c75a901af6bc4ddabd6f2f28c /llvm/lib/Target/X86/X86RegisterInfo.td | |
| parent | f65dcba83ce5035ab88a85fe17628b447eb56e1b (diff) | |
| download | src-77fc4c146f0870ffb09c1afb823ccbe742c5e6ff.tar.gz src-77fc4c146f0870ffb09c1afb823ccbe742c5e6ff.zip | |
Vendor import of llvm-project main llvmorg-14-init-13186-g0c553cc1af2e.vendor/llvm-project/llvmorg-14-init-13186-g0c553cc1af2e
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterInfo.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index d835f452b67e..1b704bcb8e08 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -430,11 +430,11 @@ def GR64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; -// GR64 - 64-bit GPRs without R8 and RIP. Could be used when emitting code for -// intrinsics, which use implict input registers. -def GR64NoR8 : RegisterClass<"X86", [i64], 64, - (add RAX, RCX, RDX, RSI, RDI, R9, R10, R11, - RBX, R14, R15, R12, R13, RBP, RSP)>; +// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when +// emitting code for intrinsics, which use implict input registers. +def GR64PLTSafe : RegisterClass<"X86", [i64], 64, + (add RAX, RCX, RDX, RSI, RDI, R8, R9, + RBX, R14, R15, R12, R13, RBP)>; // Segment registers for use by MOV instructions (and others) that have a // segment register as one operand. Always contain a 16-bit segment |