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author | Dimitry Andric <dim@FreeBSD.org> | 2021-02-16 20:13:02 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2021-02-16 20:13:02 +0000 |
commit | b60736ec1405bb0a8dd40989f67ef4c93da068ab (patch) | |
tree | 5c43fbb7c9fc45f0f87e0e6795a86267dbd12f9d /llvm/lib/Target/RISCV/RISCVInstrFormats.td | |
parent | cfca06d7963fa0909f90483b42a6d7d194d01e08 (diff) | |
download | src-b60736ec1405bb0a8dd40989f67ef4c93da068ab.tar.gz src-b60736ec1405bb0a8dd40989f67ef4c93da068ab.zip |
Vendor import of llvm-project main 8e464dd76bef, the last commit beforevendor/llvm-project/llvmorg-12-init-17869-g8e464dd76bef
the upstream release/12.x branch was created.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVInstrFormats.td')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrFormats.td | 85 |
1 files changed, 73 insertions, 12 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index a47945a6a515..7be74b79d99b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -49,18 +49,61 @@ def InstFormatCB : InstFormat<15>; def InstFormatCJ : InstFormat<16>; def InstFormatOther : InstFormat<17>; -class RISCVVConstraint<bits<4> val> { - bits<4> Value = val; +class RISCVVConstraint<bits<3> val> { + bits<3> Value = val; } -def NoConstraint : RISCVVConstraint<0>; -def WidenV : RISCVVConstraint<1>; -def WidenW : RISCVVConstraint<2>; -def WidenCvt : RISCVVConstraint<3>; -def Narrow : RISCVVConstraint<4>; -def Iota : RISCVVConstraint<5>; -def SlideUp : RISCVVConstraint<6>; -def Vrgather : RISCVVConstraint<7>; -def Vcompress : RISCVVConstraint<8>; +def NoConstraint : RISCVVConstraint<0b000>; +def VS2Constraint : RISCVVConstraint<0b001>; +def VS1Constraint : RISCVVConstraint<0b010>; +def VMConstraint : RISCVVConstraint<0b100>; + +// Illegal instructions: +// +// * The destination vector register group for a masked vector instruction +// cannot overlap the source mask register (v0), unless the destination vector +// register is being written with a mask value (e.g., comparisons) or the +// scalar result of a reduction. +// +// * Widening: The destination EEW is greater than the source EEW, the source +// EMUL is at least 1. The destination vector register group cannot overlap +// with the source vector register groups besides the highest-numbered part of +// the destination register group. +// +// * Narrowing: The destination EEW is smaller than the source EEW. The +// destination vector register group cannot overlap with the source vector +// register groups besides the lowest-numbered part of the source register +// group. +// +// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the +// source register and, if masked, cannot overlap the mask register ('v0'). +// +// * viota: The destination register cannot overlap the source register and, +// if masked, cannot overlap the mask register ('v0'). +// +// * v[f]slide[1]up: The destination vector register group for vslideup cannot +// overlap the source vector register group. +// +// * vrgather: The destination vector register group cannot overlap with the +// source vector register groups. +// +// * vcompress: The destination vector register group cannot overlap the +// source vector register group or the source mask register +def WidenV : RISCVVConstraint<!or(VS2Constraint.Value, + VS1Constraint.Value, + VMConstraint.Value)>; +def WidenW : RISCVVConstraint<!or(VS1Constraint.Value, + VMConstraint.Value)>; +def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value, + VMConstraint.Value)>; +def Iota : RISCVVConstraint<!or(VS2Constraint.Value, + VMConstraint.Value)>; +def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value, + VMConstraint.Value)>; +def Vrgather : RISCVVConstraint<!or(VS2Constraint.Value, + VS1Constraint.Value, + VMConstraint.Value)>; +def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value, + VS1Constraint.Value)>; // The following opcode names match those given in Table 19.1 in the // RISC-V User-level ISA specification ("RISC-V base opcode map"). @@ -116,7 +159,25 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr, // Defaults RISCVVConstraint RVVConstraint = NoConstraint; - let TSFlags{8-5} = RVVConstraint.Value; + let TSFlags{7-5} = RVVConstraint.Value; + + bits<3> VLMul = 0; + let TSFlags{10-8} = VLMul; + + bit HasDummyMask = 0; + let TSFlags{11} = HasDummyMask; + + bit WritesElement0 = 0; + let TSFlags{12} = WritesElement0; + + bit HasMergeOp = 0; + let TSFlags{13} = HasMergeOp; + + bit HasSEWOp = 0; + let TSFlags{14} = HasSEWOp; + + bit HasVLOp = 0; + let TSFlags{15} = HasVLOp; } // Pseudo instructions |