diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/Target/Mips/MipsMSAInstrInfo.td | |
parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
download | src-cfca06d7963fa0909f90483b42a6d7d194d01e08.tar.gz src-cfca06d7963fa0909f90483b42a6d7d194d01e08.zip |
Vendor import of llvm-project master 2e10b7a39b9, the last commit beforevendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9vendor/llvm-project/master
the llvmorg-12-init tag, from which release/11.x was branched.
Notes
Notes:
svn path=/vendor/llvm-project/master/; revision=363578
svn path=/vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9/; revision=363579; tag=vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMSAInstrInfo.td')
-rw-r--r-- | llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index 0fef518c240e..3e32574596ca 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -2339,6 +2339,16 @@ class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; +class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : + PseudoSE<(outs RO:$dst), (ins PtrRC:$ptr, GPR32:$imm), + [(set RO:$dst, (intrinsic iPTR:$ptr, GPR32:$imm))]> { + let hasNoSchedulingInfo = 1; + let usesCustomInserter = 1; +} + +def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>; +def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>; + class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs RORD:$rd); @@ -2671,6 +2681,16 @@ class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3, addrimm10lsl3>; +class MSA_STORE_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : + PseudoSE<(outs), (ins RO:$dst, PtrRC:$ptr, GPR32:$imm), + [(intrinsic RO:$dst, iPTR:$ptr, GPR32:$imm)]> { + let hasNoSchedulingInfo = 1; + let usesCustomInserter = 1; +} + +def STR_D : MSA_STORE_PSEUDO_BASE<int_mips_str_d, MSA128DOpnd>; +def STR_W : MSA_STORE_PSEUDO_BASE<int_mips_str_w, MSA128WOpnd>; + class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, MSA128BOpnd>; class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, |