Vendor import of llvm-project main 88e66fa60ae5, the last commit beforevendor/llvm-project/llvmorg-13-init-16847-g88e66fa60ae5vendor/llvm-project/llvmorg-12.0.1-rc2-0-ge7dac564cd0evendor/llvm-project/llvmorg-12.0.1-0-gfed41342a82f

the upstream release/13.x branch was created.

1 files changed, 7 insertions, 10 deletions

diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 8a847eaf6618..e963185eaeaa 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -228,14 +228,13 @@ private:
 
   unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
                            const TargetRegisterClass *RC,
-                           unsigned Op0, bool Op0IsKill,
-                           unsigned Op1, bool Op1IsKill);
+                           unsigned Op0, unsigned Op1);
 
   // for some reason, this default is not generated by tablegen
   // so we explicitly generate it here.
   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
-                             unsigned Op0, bool Op0IsKill, uint64_t imm1,
-                             uint64_t imm2, unsigned Op3, bool Op3IsKill) {
+                             unsigned Op0, uint64_t imm1, uint64_t imm2,
+                             unsigned Op3) {
     return 0;
   }
 
@@ -2122,8 +2121,7 @@ void MipsFastISel::simplifyAddress(Address &Addr) {
 
 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
                                        const TargetRegisterClass *RC,
-                                       unsigned Op0, bool Op0IsKill,
-                                       unsigned Op1, bool Op1IsKill) {
+                                       unsigned Op0, unsigned Op1) {
   // We treat the MUL instruction in a special way because it clobbers
   // the HI0 & LO0 registers. The TableGen definition of this instruction can
   // mark these registers only as implicitly defined. As a result, the
@@ -2136,15 +2134,14 @@ unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
-      .addReg(Op0, getKillRegState(Op0IsKill))
-      .addReg(Op1, getKillRegState(Op1IsKill))
+      .addReg(Op0)
+      .addReg(Op1)
       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
     return ResultReg;
   }
 
-  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
-                                   Op1IsKill);
+  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op1);
 }
 
 namespace llvm {