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author | Dimitry Andric <dim@FreeBSD.org> | 2021-12-02 21:02:54 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2021-12-02 21:02:54 +0000 |
commit | f65dcba83ce5035ab88a85fe17628b447eb56e1b (patch) | |
tree | 35f37bb72b3cfc6060193e66c76ee7c9478969b0 /llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | |
parent | 846a2208a8ab099f595fe7e8b2e6d54a7b5e67fb (diff) | |
download | src-f65dcba83ce5035ab88a85fe17628b447eb56e1b.tar.gz src-f65dcba83ce5035ab88a85fe17628b447eb56e1b.zip |
Vendor import of llvm-project main llvmorg-14-init-11187-g222442ec2d71.vendor/llvm-project/llvmorg-14-init-11187-g222442ec2d71
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 2b83a292db76..bb2859c766c2 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -3274,7 +3274,8 @@ bool ARMDAGToDAGISel::tryFP_TO_INT(SDNode *N, SDLoc dl) { return false; unsigned int ScalarBits = Type.getScalarSizeInBits(); - bool IsUnsigned = N->getOpcode() == ISD::FP_TO_UINT; + bool IsUnsigned = N->getOpcode() == ISD::FP_TO_UINT || + N->getOpcode() == ISD::FP_TO_UINT_SAT; SDNode *Node = N->getOperand(0).getNode(); // floating-point to fixed-point with one fractional bit gets turned into an @@ -3764,6 +3765,8 @@ void ARMDAGToDAGISel::Select(SDNode *N) { break; case ISD::FP_TO_UINT: case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT_SAT: + case ISD::FP_TO_SINT_SAT: if (tryFP_TO_INT(N, dl)) return; break; |