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| author | Dimitry Andric <dim@FreeBSD.org> | 2022-01-27 22:06:42 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-01-27 22:06:42 +0000 |
| commit | 6f8fc217eaa12bf657be1c6468ed9938d10168b3 (patch) | |
| tree | a1fd89b864d9b93e2ad68fe1dcf7afee2e3c8d76 /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 77fc4c146f0870ffb09c1afb823ccbe742c5e6ff (diff) | |
| download | src-6f8fc217eaa12bf657be1c6468ed9938d10168b3.tar.gz src-6f8fc217eaa12bf657be1c6468ed9938d10168b3.zip | |
Vendor import of llvm-project main llvmorg-14-init-17616-g024a1fab5c35.vendor/llvm-project/llvmorg-14-init-17616-g024a1fab5c35
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index fa244786a80d..2f083561bbd4 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -1144,7 +1144,7 @@ static bool determineFPRegsToClear(const MachineInstr &MI, if (!Op.isReg()) continue; - unsigned Reg = Op.getReg(); + Register Reg = Op.getReg(); if (Op.isDef()) { if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || (Reg >= ARM::D0 && Reg <= ARM::D15) || @@ -1356,7 +1356,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8( std::vector<unsigned> NonclearedFPRegs; for (const MachineOperand &Op : MBBI->operands()) { if (Op.isReg() && Op.isUse()) { - unsigned Reg = Op.getReg(); + Register Reg = Op.getReg(); assert(!ARM::DPRRegClass.contains(Reg) || ARM::DPR_VFP2RegClass.contains(Reg)); assert(!ARM::QPRRegClass.contains(Reg)); @@ -1451,9 +1451,9 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8( // restore FPSCR from stack and clear bits 0-4, 7, 28-31 // The other bits are program global according to the AAPCS if (passesFPReg) { - BuildMI(MBB, MBBI, DL, TII->get(ARM::t2LDRi8), SpareReg) + BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg) .addReg(ARM::SP) - .addImm(0x40) + .addImm(0x10) .add(predOps(ARMCC::AL)); BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) .addReg(SpareReg) @@ -1543,7 +1543,7 @@ void ARMExpandPseudo::CMSERestoreFPRegsV8( std::vector<unsigned> NonclearedFPRegs; for (const MachineOperand &Op : MBBI->operands()) { if (Op.isReg() && Op.isDef()) { - unsigned Reg = Op.getReg(); + Register Reg = Op.getReg(); assert(!ARM::DPRRegClass.contains(Reg) || ARM::DPR_VFP2RegClass.contains(Reg)); assert(!ARM::QPRRegClass.contains(Reg)); @@ -1663,7 +1663,7 @@ static bool definesOrUsesFPReg(const MachineInstr &MI) { for (const MachineOperand &Op : MI.operands()) { if (!Op.isReg()) continue; - unsigned Reg = Op.getReg(); + Register Reg = Op.getReg(); if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || (Reg >= ARM::D0 && Reg <= ARM::D15) || (Reg >= ARM::S0 && Reg <= ARM::S31)) @@ -2201,7 +2201,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, } case ARM::tBLXNS_CALL: { DebugLoc DL = MBBI->getDebugLoc(); - unsigned JumpReg = MBBI->getOperand(0).getReg(); + Register JumpReg = MBBI->getOperand(0).getReg(); // Figure out which registers are live at the point immediately before the // call. When we indiscriminately push a set of registers, the live |