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author	Dimitry Andric <dim@FreeBSD.org>	2020-01-17 20:45:01 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2020-01-17 20:45:01 +0000
commit	706b4fc47bbc608932d3b491ae19a3b9cde9497b (patch)
tree	4adf86a776049cbf7f69a1929c4babcbbef925eb /llvm/lib/Target/ARM/ARM.td
parent	7cc9cf2bf09f069cb2dd947ead05d0b54301fb71 (diff)
download	src-706b4fc47bbc608932d3b491ae19a3b9cde9497b.tar.gz src-706b4fc47bbc608932d3b491ae19a3b9cde9497b.zip

Vendor import of llvm-project master e26a78e70, the last commit beforevendor/llvm-project/llvmorg-10-init-17466-ge26a78e7085

the llvmorg-11-init tag, from which release/10.x was branched.

Notes

Notes: svn path=/vendor/llvm-project/master/; revision=356843 svn path=/vendor/llvm-project/llvmorg-10-init-17466-ge26a78e7085/; revision=356844; tag=vendor/llvm-project/llvmorg-10-init-17466-ge26a78e7085

Diffstat (limited to 'llvm/lib/Target/ARM/ARM.td')

-rw-r--r--

llvm/lib/Target/ARM/ARM.td

1 files changed, 18 insertions, 14 deletions

diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index fed4cb2b9316..380eaa863689 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td

@@ -303,6 +303,10 @@ def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",

def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",

"Disable VFP / NEON MAC instructions">;

+// VFPv4 added VFMA instructions that can similar be fast or slow.

+def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true",

+ "Disable VFP / NEON FMA instructions">;

// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.

def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",

"HasVMLxForwarding", "true",

@@ -415,10 +419,6 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",

"DisablePostRAScheduler", "true",

"Don't schedule again after register allocation">;

-// Enable use of alias analysis during code generation

-def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",

- "Use alias analysis during codegen">;

// Armv8.5-A extensions

def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",

@@ -584,7 +584,6 @@ def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",

"Samsung Exynos processors",

[FeatureZCZeroing,

FeatureUseWideStrideVFP,

- FeatureUseAA,

FeatureSplatVFPToNeon,

FeatureSlowVGETLNi32,

FeatureSlowVDUP32,

@@ -593,6 +592,7 @@ def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",

FeatureHWDivThumb,

FeatureHWDivARM,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureHasRetAddrStack,

FeatureFuseLiterals,

FeatureFuseAES,

@@ -923,6 +923,7 @@ def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,

FeatureTrustZone,

FeatureSlowFPBrcc,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureVMLxForwarding,

FeatureMP,

FeatureVFP4]>;

@@ -933,6 +934,7 @@ def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,

FeatureSlowFPBrcc,

FeatureHasVMLxHazards,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureVMLxForwarding,

FeatureMP,

FeatureVFP4,

@@ -945,6 +947,7 @@ def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,

FeatureSlowFPBrcc,

FeatureHasVMLxHazards,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureVMLxForwarding]>;

def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,

@@ -1014,6 +1017,7 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,

FeatureAvoidPartialCPSR,

FeatureAvoidMOVsShOp,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureHasVMLxHazards,

FeatureProfUnpredicate,

FeaturePrefISHSTBarrier,

@@ -1032,6 +1036,7 @@ def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,

FeatureHasRetAddrStack,

FeatureSlowFPBrcc,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureVFP3_D16,

FeatureAvoidPartialCPSR]>;

@@ -1041,6 +1046,7 @@ def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,

FeatureSlowFPBrcc,

FeatureHWDivARM,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureAvoidPartialCPSR]>;

def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,

@@ -1051,6 +1057,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,

FeatureSlowFPBrcc,

FeatureHWDivARM,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureAvoidPartialCPSR]>;

def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,

@@ -1061,27 +1068,26 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,

FeatureSlowFPBrcc,

FeatureHWDivARM,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureAvoidPartialCPSR]>;

def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,

ProcM3,

FeaturePrefLoopAlign32,

FeatureUseMISched,

- FeatureUseAA,

FeatureHasNoBranchPredictor]>;

def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,

ProcM3,

FeatureUseMISched,

- FeatureUseAA,

FeatureHasNoBranchPredictor]>;

def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,

FeatureVFP4_D16_SP,

FeaturePrefLoopAlign32,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureUseMISched,

- FeatureUseAA,

FeatureHasNoBranchPredictor]>;

def : ProcNoItin<"cortex-m7", [ARMv7em,

@@ -1095,8 +1101,8 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,

FeatureFPARMv8_D16_SP,

FeaturePrefLoopAlign32,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureUseMISched,

- FeatureUseAA,

FeatureHasNoBranchPredictor]>;

def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,

@@ -1104,8 +1110,8 @@ def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,

FeatureFPARMv8_D16_SP,

FeaturePrefLoopAlign32,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureUseMISched,

- FeatureUseAA,

FeatureHasNoBranchPredictor]>;

@@ -1192,13 +1198,12 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,

FeatureAvoidPartialCPSR,

FeatureAvoidMOVsShOp,

FeatureHasSlowFPVMLx,

+ FeatureHasSlowFPVFMx,

FeatureCrypto,

FeatureUseMISched,

FeatureZCZeroing,

FeatureNoPostRASched]>;

-def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>;

-def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>;

def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>;

def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos,

FeatureFullFP16,

@@ -1215,8 +1220,7 @@ def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,

def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,

FeatureUseMISched,

- FeatureFPAO,

- FeatureUseAA]>;

+ FeatureFPAO]>;

//===----------------------------------------------------------------------===//

// Register File Description