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| author | Dimitry Andric <dim@FreeBSD.org> | 2021-07-29 20:15:26 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-07-29 20:15:26 +0000 |
| commit | 344a3780b2e33f6ca763666c380202b18aab72a3 (patch) | |
| tree | f0b203ee6eb71d7fdd792373e3c81eb18d6934dd /llvm/lib/Target/ARM/ARM.td | |
| parent | b60736ec1405bb0a8dd40989f67ef4c93da068ab (diff) | |
| download | src-344a3780b2e33f6ca763666c380202b18aab72a3.tar.gz src-344a3780b2e33f6ca763666c380202b18aab72a3.zip | |
Vendor import of llvm-project main 88e66fa60ae5, the last commit beforevendor/llvm-project/llvmorg-13-init-16847-g88e66fa60ae5vendor/llvm-project/llvmorg-12.0.1-rc2-0-ge7dac564cd0evendor/llvm-project/llvmorg-12.0.1-0-gfed41342a82f
the upstream release/13.x branch was created.
Diffstat (limited to 'llvm/lib/Target/ARM/ARM.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 3d0a0bf7f8c3..5c1bed14c941 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -573,8 +573,9 @@ def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", "HardenSlsBlr", "true", "Harden against straight line speculation across indirect calls">; - - +def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", + "HardenSlsNoComdat", "true", + "Generate thunk code for SLS mitigation in the normal text section">; //===----------------------------------------------------------------------===// // ARM Processor subtarget features. @@ -852,7 +853,7 @@ def ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, FeatureCRC, FeatureRAS, FeatureDotProd]>; -def ARMv87a : Architecture<"armv8.7-a", "ARMv86a", [HasV8_7aOps, +def ARMv87a : Architecture<"armv8.7-a", "ARMv87a", [HasV8_7aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, @@ -1000,12 +1001,15 @@ def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, FeatureVFP2, FeatureHasSlowFPVMLx]>; -def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; -def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; -def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; -def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; +def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m, + FeatureHasNoBranchPredictor]>; +def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m, + FeatureHasNoBranchPredictor]>; +def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m, + FeatureHasNoBranchPredictor]>; +def : Processor<"sc000", ARMV6Itineraries, [ARMv6m, + FeatureHasNoBranchPredictor]>; -def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, FeatureVFP2, @@ -1199,7 +1203,8 @@ def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, FeatureUseMISched]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, - FeatureNoMovt]>; + FeatureNoMovt, + FeatureHasNoBranchPredictor]>; def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, FeatureDSP, |