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author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
download | src-cfca06d7963fa0909f90483b42a6d7d194d01e08.tar.gz src-cfca06d7963fa0909f90483b42a6d7d194d01e08.zip |
Vendor import of llvm-project master 2e10b7a39b9, the last commit beforevendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9vendor/llvm-project/master
the llvmorg-12-init tag, from which release/11.x was branched.
Notes
Notes:
svn path=/vendor/llvm-project/master/; revision=363578
svn path=/vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9/; revision=363579; tag=vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineRegisterInfo.cpp | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index b88d4ea462ef..4c733738840a 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -55,18 +55,18 @@ MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) /// setRegClass - Set the register class of the specified virtual register. /// void -MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { +MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); VRegInfo[Reg].first = RC; } -void MachineRegisterInfo::setRegBank(unsigned Reg, +void MachineRegisterInfo::setRegBank(Register Reg, const RegisterBank &RegBank) { VRegInfo[Reg].first = &RegBank; } static const TargetRegisterClass * -constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, +constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs) { if (OldRC == RC) @@ -82,15 +82,15 @@ constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, } const TargetRegisterClass * -MachineRegisterInfo::constrainRegClass(unsigned Reg, +MachineRegisterInfo::constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); } bool -MachineRegisterInfo::constrainRegAttrs(unsigned Reg, - unsigned ConstrainingReg, +MachineRegisterInfo::constrainRegAttrs(Register Reg, + Register ConstrainingReg, unsigned MinNumRegs) { const LLT RegTy = getType(Reg); const LLT ConstrainingRegTy = getType(ConstrainingReg); @@ -119,7 +119,7 @@ MachineRegisterInfo::constrainRegAttrs(unsigned Reg, } bool -MachineRegisterInfo::recomputeRegClass(unsigned Reg) { +MachineRegisterInfo::recomputeRegClass(Register Reg) { const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); const TargetRegisterClass *OldRC = getRegClass(Reg); const TargetRegisterClass *NewRC = @@ -143,8 +143,8 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg) { return true; } -unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { - unsigned Reg = Register::index2VirtReg(getNumVirtRegs()); +Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { + Register Reg = Register::index2VirtReg(getNumVirtRegs()); VRegInfo.grow(Reg); RegAllocHints.grow(Reg); insertVRegByName(Name, Reg); @@ -162,7 +162,7 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, "Virtual register RegClass must be allocatable."); // New virtual register number. - unsigned Reg = createIncompleteVirtualRegister(Name); + Register Reg = createIncompleteVirtualRegister(Name); VRegInfo[Reg].first = RegClass; if (TheDelegate) TheDelegate->MRI_NoteNewVirtualRegister(Reg); @@ -171,7 +171,7 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, StringRef Name) { - unsigned Reg = createIncompleteVirtualRegister(Name); + Register Reg = createIncompleteVirtualRegister(Name); VRegInfo[Reg].first = VRegInfo[VReg].first; setType(Reg, getType(VReg)); if (TheDelegate) @@ -179,7 +179,7 @@ Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, return Reg; } -void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) { +void MachineRegisterInfo::setType(Register VReg, LLT Ty) { VRegToType.grow(VReg); VRegToType[VReg] = Ty; } @@ -187,7 +187,7 @@ void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) { Register MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) { // New virtual register number. - unsigned Reg = createIncompleteVirtualRegister(Name); + Register Reg = createIncompleteVirtualRegister(Name); // FIXME: Should we use a dummy register class? VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); setType(Reg, Ty); @@ -202,7 +202,7 @@ void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); } void MachineRegisterInfo::clearVirtRegs() { #ifndef NDEBUG for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); + Register Reg = Register::index2VirtReg(i); if (!VRegInfo[Reg].second) continue; verifyUseList(Reg); @@ -214,7 +214,7 @@ void MachineRegisterInfo::clearVirtRegs() { I.second = 0; } -void MachineRegisterInfo::verifyUseList(unsigned Reg) const { +void MachineRegisterInfo::verifyUseList(Register Reg) const { #ifndef NDEBUG bool Valid = true; for (MachineOperand &M : reg_operands(Reg)) { @@ -377,7 +377,7 @@ void MachineRegisterInfo::moveOperands(MachineOperand *Dst, /// except that it also changes any definitions of the register as well. /// If ToReg is a physical register we apply the sub register to obtain the /// final/proper physical register. -void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { +void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { assert(FromReg != ToReg && "Cannot replace a reg with itself"); const TargetRegisterInfo *TRI = getTargetRegisterInfo(); @@ -397,7 +397,7 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { /// getVRegDef - Return the machine instr that defines the specified virtual /// register or null if none is found. This assumes that the code is in SSA /// form, so there should only be one definition. -MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { +MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const { // Since we are in SSA form, we can use the first definition. def_instr_iterator I = def_instr_begin(Reg); assert((I.atEnd() || std::next(I) == def_instr_end()) && @@ -408,7 +408,7 @@ MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { /// getUniqueVRegDef - Return the unique machine instr that defines the /// specified virtual register or null if none is found. If there are /// multiple definitions or no definition, return null. -MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { +MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { if (def_empty(Reg)) return nullptr; def_instr_iterator I = def_instr_begin(Reg); if (std::next(I) != def_instr_end()) @@ -416,14 +416,14 @@ MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { return &*I; } -bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { +bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const { use_nodbg_iterator UI = use_nodbg_begin(RegNo); if (UI == use_nodbg_end()) return false; return ++UI == use_nodbg_end(); } -bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const { +bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const { use_instr_nodbg_iterator UI = use_instr_nodbg_begin(RegNo); if (UI == use_instr_nodbg_end()) return false; @@ -434,34 +434,34 @@ bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const { /// clear the kill flag from the MachineOperand. This function is used by /// optimization passes which extend register lifetimes and need only /// preserve conservative kill flag information. -void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { +void MachineRegisterInfo::clearKillFlags(Register Reg) const { for (MachineOperand &MO : use_operands(Reg)) MO.setIsKill(false); } -bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { +bool MachineRegisterInfo::isLiveIn(Register Reg) const { for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) - if (I->first == Reg || I->second == Reg) + if ((Register)I->first == Reg || I->second == Reg) return true; return false; } /// getLiveInPhysReg - If VReg is a live-in virtual register, return the /// corresponding live-in physical register. -unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { +MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) if (I->second == VReg) return I->first; - return 0; + return MCRegister(); } /// getLiveInVirtReg - If PReg is a live-in physical register, return the /// corresponding live-in physical register. -unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { +Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const { for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) if (I->first == PReg) return I->second; - return 0; + return Register(); } /// EmitLiveInCopies - Emit copies to initialize livein virtual registers @@ -496,7 +496,7 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, } } -LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const { +LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const { // Lane masks are only defined for vregs. assert(Register::isVirtualRegister(Reg)); const TargetRegisterClass &TRC = *getRegClass(Reg); @@ -504,7 +504,7 @@ LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const { } #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) -LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const { +LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { for (MachineInstr &I : use_instructions(Reg)) I.dump(); } @@ -516,7 +516,7 @@ void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { "Invalid ReservedRegs vector from target"); } -bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { +bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { assert(Register::isPhysicalRegister(PhysReg)); const TargetRegisterInfo *TRI = getTargetRegisterInfo(); @@ -533,7 +533,7 @@ bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { } bool -MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const { +MachineRegisterInfo::isCallerPreservedOrConstPhysReg(MCRegister PhysReg) const { const TargetRegisterInfo *TRI = getTargetRegisterInfo(); return isConstantPhysReg(PhysReg) || TRI->isCallerPreservedPhysReg(PhysReg, *MF); @@ -542,7 +542,7 @@ MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const { /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the /// specified register as undefined which causes the DBG_VALUE to be /// deleted during LiveDebugVariables analysis. -void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { +void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const { // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) MachineRegisterInfo::use_instr_iterator nextI; for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); @@ -550,7 +550,7 @@ void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { nextI = std::next(I); // I is invalidated by the setReg MachineInstr *UseMI = &*I; if (UseMI->isDebugValue()) - UseMI->getOperand(0).setReg(0U); + UseMI->getDebugOperandForReg(Reg)->setReg(0U); } } @@ -583,7 +583,7 @@ static bool isNoReturnDef(const MachineOperand &MO) { !Called->hasFnAttribute(Attribute::NoUnwind)); } -bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg, +bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef) const { if (UsedPhysRegMask.test(PhysReg)) return true; @@ -598,7 +598,7 @@ bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg, return false; } -bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const { +bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const { if (UsedPhysRegMask.test(PhysReg)) return true; const TargetRegisterInfo *TRI = getTargetRegisterInfo(); @@ -610,7 +610,7 @@ bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const { return false; } -void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) { +void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { const TargetRegisterInfo *TRI = getTargetRegisterInfo(); assert(Reg && (Reg < TRI->getNumRegs()) && |