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author | David Schultz <das@FreeBSD.org> | 2005-03-16 19:03:46 +0000 |
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committer | David Schultz <das@FreeBSD.org> | 2005-03-16 19:03:46 +0000 |
commit | 10b01832c3672b9a63edd86f74f1167dbc33c7f6 (patch) | |
tree | ed1345d1aaf08f9b2af1cfc6cc10e15b82d917d1 /lib/msun/powerpc/fenv.h | |
parent | c4bf1e9092058df57b90b2090eb4591d7158c521 (diff) | |
download | src-10b01832c3672b9a63edd86f74f1167dbc33c7f6.tar.gz src-10b01832c3672b9a63edd86f74f1167dbc33c7f6.zip |
Replace fegetmask() and fesetmask() with feenableexcept(),
fedisableexcept(), and fegetexcept(). These two sets of routines
provide the same functionality. I implemented the former as an
undocumented internal interface to make the regression test easier to
write. However, fe(enable|disable|get)except() is already part of
glibc, and I would like to avoid gratuitous differences. The only
major flaw in the glibc API is that there's no good way to report
errors on processors that don't support all the unmasked exceptions.
Notes
Notes:
svn path=/head/; revision=143708
Diffstat (limited to 'lib/msun/powerpc/fenv.h')
-rw-r--r-- | lib/msun/powerpc/fenv.h | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/lib/msun/powerpc/fenv.h b/lib/msun/powerpc/fenv.h index ed9d935aa1dd..3010472e14f3 100644 --- a/lib/msun/powerpc/fenv.h +++ b/lib/msun/powerpc/fenv.h @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2004 David Schultz <das@FreeBSD.ORG> + * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -222,21 +222,33 @@ feupdateenv(const fenv_t *__envp) #if __BSD_VISIBLE static __inline int -fesetmask(int __mask) +feenableexcept(int __mask) { union __fpscr __r; fenv_t __oldmask; __mffs(&__r.__d); __oldmask = __r.__bits.__reg; - __r.__bits.__reg &= ~_ENABLE_MASK; - __r.__bits.__reg |= __mask >> _FPUSW_SHIFT; + __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; __mtfsf(__r.__d); return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); } static __inline int -fegetmask(void) +fedisableexcept(int __mask) +{ + union __fpscr __r; + fenv_t __oldmask; + + __mffs(&__r.__d); + __oldmask = __r.__bits.__reg; + __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); + __mtfsf(__r.__d); + return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); +} + +static __inline int +fegetexcept(void) { union __fpscr __r; |