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author | Dimitry Andric <dim@FreeBSD.org> | 2011-07-17 15:36:56 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2011-07-17 15:36:56 +0000 |
commit | 411bd29eea3c360d5b48a18a17b5e87f5671af0e (patch) | |
tree | c8086addb211fa670a9d2b1038d8c2e453229755 /lib/Target/TargetRegisterInfo.cpp | |
parent | 56fe8f14099930935e3870e3e823c322a85c1c89 (diff) | |
download | src-411bd29eea3c360d5b48a18a17b5e87f5671af0e.tar.gz src-411bd29eea3c360d5b48a18a17b5e87f5671af0e.zip |
Vendor import of llvm trunk r135360:vendor/llvm/llvm-r135360
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=224133
svn path=/vendor/llvm/llvm-r135360/; revision=224134; tag=vendor/llvm/llvm-r135360
Diffstat (limited to 'lib/Target/TargetRegisterInfo.cpp')
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 24 |
1 files changed, 7 insertions, 17 deletions
diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index 1c3f2dda33c7..90a8f8d8fdcc 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -20,21 +20,11 @@ using namespace llvm; -TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, - const char *const *subregindexnames, - int CFSO, int CFDO, - const unsigned* subregs, const unsigned subregsize, - const unsigned* aliases, const unsigned aliasessize) - : SubregHash(subregs), SubregHashSize(subregsize), - AliasesHash(aliases), AliasesHashSize(aliasessize), - Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR), + const char *const *subregindexnames) + : InfoDesc(ID), SubRegIndexNames(subregindexnames), RegClassBegin(RCB), RegClassEnd(RCE) { - assert(isPhysicalRegister(NumRegs) && - "Target has too many physical registers!"); - - CallFrameSetupOpcode = CFSO; - CallFrameDestroyOpcode = CFDO; } TargetRegisterInfo::~TargetRegisterInfo() {} @@ -83,14 +73,14 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) - R.set(*I); + ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); + for (unsigned i = 0; i != Order.size(); ++i) + R.set(Order[i]); } BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC) const { - BitVector Allocatable(NumRegs); + BitVector Allocatable(getNumRegs()); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); } else { |