diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /lib/Target/Mips/MipsRegisterInfo.td | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
| download | src-01095a5d43bbfde13731688ddcf6048ebb8b7721.tar.gz src-01095a5d43bbfde13731688ddcf6048ebb8b7721.zip | |
Vendor import of llvm release_39 branch r276489:vendor/llvm/llvm-release_39-r276489
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=303231
svn path=/vendor/llvm/llvm-release_39-r276489/; revision=303232; tag=vendor/llvm/llvm-release_39-r276489
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 02bcac5a3ddb..cfce7c8e6533 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -330,6 +330,12 @@ def GPR64 : RegisterClass<"Mips", [i64], 64, (add // Reserved K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; +def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add + // Callee save + S0_64, S1_64, + // Return Values and Arguments + V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>; + def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments V0, V1, A0, A1, A2, A3, @@ -447,6 +453,13 @@ def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>, Unallocatable; +// Stack pointer and global pointer classes for instructions that are limited +// to a single register such as lwgp/lwsp in microMIPS. +def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; +def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable; +def GP32 : RegisterClass<"Mips", [i32], 32, (add GP)>, Unallocatable; +def GP64 : RegisterClass<"Mips", [i64], 64, (add GP_64)>, Unallocatable; + // Octeon multiplier and product registers def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>, Unallocatable; |