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author | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
commit | eb11fae6d08f479c0799db45860a98af528fa6e7 (patch) | |
tree | 44d492a50c8c1a7eb8e2d17ea3360ec4d066f042 /lib/Target/Mips/Mips.td | |
parent | b8a2042aa938069e862750553db0e4d82d25822c (diff) | |
download | src-eb11fae6d08f479c0799db45860a98af528fa6e7.tar.gz src-eb11fae6d08f479c0799db45860a98af528fa6e7.zip |
Vendor import of llvm trunk r338150:vendor/llvm/llvm-trunk-r338150
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=336809
svn path=/vendor/llvm/llvm-trunk-r338150/; revision=336814; tag=vendor/llvm/llvm-trunk-r338150
Diffstat (limited to 'lib/Target/Mips/Mips.td')
-rw-r--r-- | lib/Target/Mips/Mips.td | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 6ceb05577538..2f3a1c399d3e 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -28,8 +28,10 @@ class PredicateControl { list<Predicate> PTRPredicates = []; // Predicates for the FGR size and layout such as IsFP64bit list<Predicate> FGRPredicates = []; - // Predicates for the instruction group membership such as ISA's and ASE's + // Predicates for the instruction group membership such as ISA's. list<Predicate> InsnPredicates = []; + // Predicate for the ASE that an instruction belongs to. + list<Predicate> ASEPredicate = []; // Predicate for marking the instruction as usable in hard-float mode only. list<Predicate> HardFloatPredicate = []; // Predicates for anything else @@ -40,6 +42,7 @@ class PredicateControl { FGRPredicates, InsnPredicates, HardFloatPredicate, + ASEPredicate, AdditionalPredicates); } @@ -56,6 +59,7 @@ include "MipsRegisterInfo.td" include "MipsSchedule.td" include "MipsInstrInfo.td" include "MipsCallingConv.td" +include "MipsRegisterBanks.td" // Avoid forward declaration issues. include "MipsScheduleP5600.td" @@ -173,6 +177,14 @@ def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">; +def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">; + +def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true", + "Mips Virtualization ASE">; + +def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true", + "Mips Global Invalidate ASE">; + def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", "microMips mode">; @@ -193,6 +205,10 @@ def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">; def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true", "Disable use of the jal instruction">; +def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard", + "UseIndirectJumpsHazard", + "true", "Use indirect jump" + " guards to prevent certain speculation based attacks">; //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// @@ -238,4 +254,5 @@ def Mips : Target { let InstructionSet = MipsInstrInfo; let AssemblyParsers = [MipsAsmParser]; let AssemblyParserVariants = [MipsAsmParserVariant]; + let AllowRegisterRenaming = 1; } |