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author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
tree | 4def12e759965de927d963ac65840d663ef9d1ea /lib/Target/Hexagon/BitTracker.cpp | |
parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
download | src-01095a5d43bbfde13731688ddcf6048ebb8b7721.tar.gz src-01095a5d43bbfde13731688ddcf6048ebb8b7721.zip |
Vendor import of llvm release_39 branch r276489:vendor/llvm/llvm-release_39-r276489
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=303231
svn path=/vendor/llvm/llvm-release_39-r276489/; revision=303232; tag=vendor/llvm/llvm-release_39-r276489
Diffstat (limited to 'lib/Target/Hexagon/BitTracker.cpp')
-rw-r--r-- | lib/Target/Hexagon/BitTracker.cpp | 220 |
1 files changed, 110 insertions, 110 deletions
diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp index ea96eb0ee10a..d052a835fbd8 100644 --- a/lib/Target/Hexagon/BitTracker.cpp +++ b/lib/Target/Hexagon/BitTracker.cpp @@ -84,87 +84,89 @@ namespace { } } -raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::BitValue &BV) { - switch (BV.Type) { - case BT::BitValue::Top: - OS << 'T'; - break; - case BT::BitValue::Zero: - OS << '0'; - break; - case BT::BitValue::One: - OS << '1'; - break; - case BT::BitValue::Ref: - OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']'; - break; +namespace llvm { + raw_ostream &operator<<(raw_ostream &OS, const BT::BitValue &BV) { + switch (BV.Type) { + case BT::BitValue::Top: + OS << 'T'; + break; + case BT::BitValue::Zero: + OS << '0'; + break; + case BT::BitValue::One: + OS << '1'; + break; + case BT::BitValue::Ref: + OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']'; + break; + } + return OS; } - return OS; -} -raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { - unsigned n = RC.Bits.size(); - OS << "{ w:" << n; - // Instead of printing each bit value individually, try to group them - // into logical segments, such as sequences of 0 or 1 bits or references - // to consecutive bits (e.g. "bits 3-5 are same as bits 7-9 of reg xyz"). - // "Start" will be the index of the beginning of the most recent segment. - unsigned Start = 0; - bool SeqRef = false; // A sequence of refs to consecutive bits. - bool ConstRef = false; // A sequence of refs to the same bit. - - for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) { - const BT::BitValue &V = RC[i]; - const BT::BitValue &SV = RC[Start]; - bool IsRef = (V.Type == BT::BitValue::Ref); - // If the current value is the same as Start, skip to the next one. - if (!IsRef && V == SV) - continue; - if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) { - if (Start+1 == i) { - SeqRef = (V.RefI.Pos == SV.RefI.Pos+1); - ConstRef = (V.RefI.Pos == SV.RefI.Pos); - } - if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start)) - continue; - if (ConstRef && V.RefI.Pos == SV.RefI.Pos) + raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { + unsigned n = RC.Bits.size(); + OS << "{ w:" << n; + // Instead of printing each bit value individually, try to group them + // into logical segments, such as sequences of 0 or 1 bits or references + // to consecutive bits (e.g. "bits 3-5 are same as bits 7-9 of reg xyz"). + // "Start" will be the index of the beginning of the most recent segment. + unsigned Start = 0; + bool SeqRef = false; // A sequence of refs to consecutive bits. + bool ConstRef = false; // A sequence of refs to the same bit. + + for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) { + const BT::BitValue &V = RC[i]; + const BT::BitValue &SV = RC[Start]; + bool IsRef = (V.Type == BT::BitValue::Ref); + // If the current value is the same as Start, skip to the next one. + if (!IsRef && V == SV) continue; + if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) { + if (Start+1 == i) { + SeqRef = (V.RefI.Pos == SV.RefI.Pos+1); + ConstRef = (V.RefI.Pos == SV.RefI.Pos); + } + if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start)) + continue; + if (ConstRef && V.RefI.Pos == SV.RefI.Pos) + continue; + } + + // The current value is different. Print the previous one and reset + // the Start. + OS << " [" << Start; + unsigned Count = i - Start; + if (Count == 1) { + OS << "]:" << SV; + } else { + OS << '-' << i-1 << "]:"; + if (SV.Type == BT::BitValue::Ref && SeqRef) + OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' + << SV.RefI.Pos+(Count-1) << ']'; + else + OS << SV; + } + Start = i; + SeqRef = ConstRef = false; } - // The current value is different. Print the previous one and reset - // the Start. OS << " [" << Start; - unsigned Count = i - Start; - if (Count == 1) { - OS << "]:" << SV; + unsigned Count = n - Start; + if (n-Start == 1) { + OS << "]:" << RC[Start]; } else { - OS << '-' << i-1 << "]:"; + OS << '-' << n-1 << "]:"; + const BT::BitValue &SV = RC[Start]; if (SV.Type == BT::BitValue::Ref && SeqRef) OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' << SV.RefI.Pos+(Count-1) << ']'; else OS << SV; } - Start = i; - SeqRef = ConstRef = false; - } + OS << " }"; - OS << " [" << Start; - unsigned Count = n - Start; - if (n-Start == 1) { - OS << "]:" << RC[Start]; - } else { - OS << '-' << n-1 << "]:"; - const BT::BitValue &SV = RC[Start]; - if (SV.Type == BT::BitValue::Ref && SeqRef) - OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' - << SV.RefI.Pos+(Count-1) << ']'; - else - OS << SV; + return OS; } - OS << " }"; - - return OS; } BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) @@ -420,7 +422,7 @@ BT::RegisterCell BT::MachineEvaluator::eIMM(int64_t V, uint16_t W) const { BT::RegisterCell BT::MachineEvaluator::eIMM(const ConstantInt *CI) const { - APInt A = CI->getValue(); + const APInt &A = CI->getValue(); uint16_t BW = A.getBitWidth(); assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); RegisterCell Res(BW); @@ -731,18 +733,18 @@ BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const { return BitMask(0, W-1); } - -bool BT::MachineEvaluator::evaluate(const MachineInstr *MI, - const CellMapType &Inputs, CellMapType &Outputs) const { - unsigned Opc = MI->getOpcode(); +bool BT::MachineEvaluator::evaluate(const MachineInstr &MI, + const CellMapType &Inputs, + CellMapType &Outputs) const { + unsigned Opc = MI.getOpcode(); switch (Opc) { case TargetOpcode::REG_SEQUENCE: { - RegisterRef RD = MI->getOperand(0); + RegisterRef RD = MI.getOperand(0); assert(RD.Sub == 0); - RegisterRef RS = MI->getOperand(1); - unsigned SS = MI->getOperand(2).getImm(); - RegisterRef RT = MI->getOperand(3); - unsigned ST = MI->getOperand(4).getImm(); + RegisterRef RS = MI.getOperand(1); + unsigned SS = MI.getOperand(2).getImm(); + RegisterRef RT = MI.getOperand(3); + unsigned ST = MI.getOperand(4).getImm(); assert(SS != ST); uint16_t W = getRegBitWidth(RD); @@ -756,8 +758,8 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr *MI, case TargetOpcode::COPY: { // COPY can transfer a smaller register into a wider one. // If that is the case, fill the remaining high bits with 0. - RegisterRef RD = MI->getOperand(0); - RegisterRef RS = MI->getOperand(1); + RegisterRef RD = MI.getOperand(0); + RegisterRef RS = MI.getOperand(1); assert(RD.Sub == 0); uint16_t WD = getRegBitWidth(RD); uint16_t WS = getRegBitWidth(RS); @@ -780,12 +782,12 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr *MI, // Main W-Z implementation. -void BT::visitPHI(const MachineInstr *PI) { - int ThisN = PI->getParent()->getNumber(); +void BT::visitPHI(const MachineInstr &PI) { + int ThisN = PI.getParent()->getNumber(); if (Trace) - dbgs() << "Visit FI(BB#" << ThisN << "): " << *PI; + dbgs() << "Visit FI(BB#" << ThisN << "): " << PI; - const MachineOperand &MD = PI->getOperand(0); + const MachineOperand &MD = PI.getOperand(0); assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition"); RegisterRef DefRR(MD); uint16_t DefBW = ME.getRegBitWidth(DefRR); @@ -796,8 +798,8 @@ void BT::visitPHI(const MachineInstr *PI) { bool Changed = false; - for (unsigned i = 1, n = PI->getNumOperands(); i < n; i += 2) { - const MachineBasicBlock *PB = PI->getOperand(i+1).getMBB(); + for (unsigned i = 1, n = PI.getNumOperands(); i < n; i += 2) { + const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB(); int PredN = PB->getNumber(); if (Trace) dbgs() << " edge BB#" << PredN << "->BB#" << ThisN; @@ -807,7 +809,7 @@ void BT::visitPHI(const MachineInstr *PI) { continue; } - RegisterRef RU = PI->getOperand(i); + RegisterRef RU = PI.getOperand(i); RegisterCell ResC = ME.getCell(RU, Map); if (Trace) dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) @@ -824,22 +826,21 @@ void BT::visitPHI(const MachineInstr *PI) { } } - -void BT::visitNonBranch(const MachineInstr *MI) { +void BT::visitNonBranch(const MachineInstr &MI) { if (Trace) { - int ThisN = MI->getParent()->getNumber(); - dbgs() << "Visit MI(BB#" << ThisN << "): " << *MI; + int ThisN = MI.getParent()->getNumber(); + dbgs() << "Visit MI(BB#" << ThisN << "): " << MI; } - if (MI->isDebugValue()) + if (MI.isDebugValue()) return; - assert(!MI->isBranch() && "Unexpected branch instruction"); + assert(!MI.isBranch() && "Unexpected branch instruction"); CellMapType ResMap; bool Eval = ME.evaluate(MI, Map, ResMap); if (Trace && Eval) { - for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) { - const MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { + const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isUse()) continue; RegisterRef RU(MO); @@ -857,8 +858,8 @@ void BT::visitNonBranch(const MachineInstr *MI) { // Iterate over all definitions of the instruction, and update the // cells accordingly. - for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) { - const MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { + const MachineOperand &MO = MI.getOperand(i); // Visit register defs only. if (!MO.isReg() || !MO.isDef()) continue; @@ -905,9 +906,8 @@ void BT::visitNonBranch(const MachineInstr *MI) { } } - -void BT::visitBranchesFrom(const MachineInstr *BI) { - const MachineBasicBlock &B = *BI->getParent(); +void BT::visitBranchesFrom(const MachineInstr &BI) { + const MachineBasicBlock &B = *BI.getParent(); MachineBasicBlock::const_iterator It = BI, End = B.end(); BranchTargetList Targets, BTs; bool FallsThrough = true, DefaultToAll = false; @@ -915,11 +915,11 @@ void BT::visitBranchesFrom(const MachineInstr *BI) { do { BTs.clear(); - const MachineInstr *MI = &*It; + const MachineInstr &MI = *It; if (Trace) - dbgs() << "Visit BR(BB#" << ThisN << "): " << *MI; - assert(MI->isBranch() && "Expecting branch instruction"); - InstrExec.insert(MI); + dbgs() << "Visit BR(BB#" << ThisN << "): " << MI; + assert(MI.isBranch() && "Expecting branch instruction"); + InstrExec.insert(&MI); bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough); if (!Eval) { // If the evaluation failed, we will add all targets. Keep going in @@ -983,11 +983,11 @@ void BT::visitUsesOf(unsigned Reg) { if (!InstrExec.count(UseI)) continue; if (UseI->isPHI()) - visitPHI(UseI); + visitPHI(*UseI); else if (!UseI->isBranch()) - visitNonBranch(UseI); + visitNonBranch(*UseI); else - visitBranchesFrom(UseI); + visitBranchesFrom(*UseI); } } @@ -1084,8 +1084,8 @@ void BT::run() { MachineBasicBlock::const_iterator It = B.begin(), End = B.end(); // Visit PHI nodes first. while (It != End && It->isPHI()) { - const MachineInstr *PI = &*It++; - InstrExec.insert(PI); + const MachineInstr &PI = *It++; + InstrExec.insert(&PI); visitPHI(PI); } @@ -1098,8 +1098,8 @@ void BT::run() { // Visit non-branch instructions. while (It != End && !It->isBranch()) { - const MachineInstr *MI = &*It++; - InstrExec.insert(MI); + const MachineInstr &MI = *It++; + InstrExec.insert(&MI); visitNonBranch(MI); } // If block end has been reached, add the fall-through edge to the queue. @@ -1114,7 +1114,7 @@ void BT::run() { } else { // Handle the remaining sequence of branches. This function will update // the work queue. - visitBranchesFrom(It); + visitBranchesFrom(*It); } } // while (!FlowQ->empty()) |