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author | Dimitry Andric <dim@FreeBSD.org> | 2017-01-02 19:17:04 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2017-01-02 19:17:04 +0000 |
commit | b915e9e0fc85ba6f398b3fab0db6a81a8913af94 (patch) | |
tree | 98b8f811c7aff2547cab8642daf372d6c59502fb /lib/CodeGen/MachineRegisterInfo.cpp | |
parent | 6421cca32f69ac849537a3cff78c352195e99f1b (diff) | |
download | src-b915e9e0fc85ba6f398b3fab0db6a81a8913af94.tar.gz src-b915e9e0fc85ba6f398b3fab0db6a81a8913af94.zip |
Vendor import of llvm trunk r290819:vendor/llvm/llvm-trunk-r290819
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=311116
svn path=/vendor/llvm/llvm-trunk-r290819/; revision=311117; tag=vendor/llvm/llvm-trunk-r290819
Diffstat (limited to 'lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r-- | lib/CodeGen/MachineRegisterInfo.cpp | 58 |
1 files changed, 37 insertions, 21 deletions
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index 613598dbe215..242cb0b80953 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -21,11 +21,16 @@ using namespace llvm; +static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, + cl::init(true), cl::desc("Enable subregister liveness tracking.")); + // Pin the vtable to this file. void MachineRegisterInfo::Delegate::anchor() {} MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) - : MF(MF), TheDelegate(nullptr), TracksSubRegLiveness(false) { + : MF(MF), TheDelegate(nullptr), + TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && + EnableSubRegLiveness) { unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); VRegInfo.reserve(256); RegAllocHints.reserve(256); @@ -88,6 +93,13 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg) { return true; } +unsigned MachineRegisterInfo::createIncompleteVirtualRegister() { + unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); + VRegInfo.grow(Reg); + RegAllocHints.grow(Reg); + return Reg; +} + /// createVirtualRegister - Create and return a new virtual register in the /// function with the specified register class. /// @@ -98,41 +110,42 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ "Virtual register RegClass must be allocatable."); // New virtual register number. - unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); - VRegInfo.grow(Reg); + unsigned Reg = createIncompleteVirtualRegister(); VRegInfo[Reg].first = RegClass; - RegAllocHints.grow(Reg); if (TheDelegate) TheDelegate->MRI_NoteNewVirtualRegister(Reg); return Reg; } -unsigned -MachineRegisterInfo::getSize(unsigned VReg) const { - VRegToSizeMap::const_iterator SizeIt = getVRegToSize().find(VReg); - return SizeIt != getVRegToSize().end() ? SizeIt->second : 0; +LLT MachineRegisterInfo::getType(unsigned VReg) const { + VRegToTypeMap::const_iterator TypeIt = getVRegToType().find(VReg); + return TypeIt != getVRegToType().end() ? TypeIt->second : LLT{}; } -void MachineRegisterInfo::setSize(unsigned VReg, unsigned Size) { - getVRegToSize()[VReg] = Size; +void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) { + // Check that VReg doesn't have a class. + assert((getRegClassOrRegBank(VReg).isNull() || + !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) && + "Can't set the size of a non-generic virtual register"); + getVRegToType()[VReg] = Ty; } unsigned -MachineRegisterInfo::createGenericVirtualRegister(unsigned Size) { - assert(Size && "Cannot create empty virtual register"); - +MachineRegisterInfo::createGenericVirtualRegister(LLT Ty) { // New virtual register number. - unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); - VRegInfo.grow(Reg); + unsigned Reg = createIncompleteVirtualRegister(); // FIXME: Should we use a dummy register class? - VRegInfo[Reg].first = static_cast<TargetRegisterClass *>(nullptr); - getVRegToSize()[Reg] = Size; - RegAllocHints.grow(Reg); + VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); + getVRegToType()[Reg] = Ty; if (TheDelegate) TheDelegate->MRI_NoteNewVirtualRegister(Reg); return Reg; } +void MachineRegisterInfo::clearVirtRegTypes() { + getVRegToType().clear(); +} + /// clearVirtRegs - Remove all virtual registers (after physreg assignment). void MachineRegisterInfo::clearVirtRegs() { #ifndef NDEBUG @@ -444,13 +457,16 @@ void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { "Invalid ReservedRegs vector from target"); } -bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, - const MachineFunction &MF) const { +bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); + const TargetRegisterInfo *TRI = getTargetRegisterInfo(); + if (TRI->isConstantPhysReg(PhysReg)) + return true; + // Check if any overlapping register is modified, or allocatable so it may be // used later. - for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true); + for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) if (!def_empty(*AI) || isAllocatable(*AI)) return false; |