OFED user-space import and update for use with Linux-4.9 compatible RDMA

kernel APIs.

List of sources used:

1) rdma-core was cloned from "https://github.com/linux-rdma/rdma-core.git"
Top commit d65138ef93af30b3ea249f3a84aa6a24ba7f8a75

2) OpenSM was cloned from git://git.openfabrics.org/~halr/opensm.git
Top commit 85f841cf209f791c89a075048a907020e924528d

3) libibmad was cloned from "git://git.openfabrics.org/~iraweiny/libibmad.git"
Tag 1.3.13 with some additional patches from Mellanox.

4) infiniband-diags was cloned from "git://git.openfabrics.org/~iraweiny/infiniband-diags.git"
Tag 1.6.7 with some additional patches from Mellanox.

Added the required Makefiles for building and installing.

Sponsored by:	Mellanox Technologies

8 files changed, 451 insertions, 120 deletions

diff --git a/contrib/ofed/include/Makefile b/contrib/ofed/include/Makefile
index ccc151c4bbd5..543b48864663 100644
--- a/contrib/ofed/include/Makefile
+++ b/contrib/ofed/include/Makefile
@@ -1,5 +1,192 @@
-.include <bsd.own.mk>
+# $FreeBSD$
 
-SUBDIR	= infiniband rdma
+IBVERBS=	${.CURDIR}/../libibverbs
+IBMAD=		${.CURDIR}/../libibmad
+IBUMAD=		${.CURDIR}/../libibumad
+IBCM=		${.CURDIR}/../libibcm
+IBND=		${.CURDIR}/../libibnetdisc
+RDMACM=		${.CURDIR}/../librdmacm
+RDMA=		${.CURDIR}/../../../sys/ofed/include/uapi/rdma
+OSM=		${.CURDIR}/../opensm/include
 
-.include <bsd.subdir.mk>
+IBINCS= \
+byteorder.h \
+byteswap.h \
+endian.h \
+types.h \
+udma_barrier.h \
+${IBVERBS}/arch.h \
+${IBVERBS}/driver.h \
+${IBVERBS}/kern-abi.h \
+${IBVERBS}/marshall.h \
+${IBVERBS}/opcode.h \
+${IBVERBS}/sa-kern-abi.h \
+${IBVERBS}/sa.h \
+${IBVERBS}/verbs.h \
+${IBUMAD}/umad.h \
+${IBUMAD}/umad_cm.h \
+${IBUMAD}/umad_sa.h \
+${IBUMAD}/umad_sm.h \
+${IBUMAD}/umad_str.h \
+${IBUMAD}/umad_types.h \
+${IBMAD}/mad.h \
+${IBMAD}/mad_osd.h \
+${IBCM}/cm.h \
+${IBCM}/cm_abi.h \
+${IBND}/ibnetdisc.h \
+${IBND}/ibnetdisc_osd.h \
+${RDMACM}/ib.h
+IBINCSDIR=	${INCLUDEDIR}/infiniband
+
+RDMAINCS= \
+${RDMACM}/rdma_cma.h \
+${RDMACM}/rdma_cma_abi.h \
+${RDMACM}/rdma_verbs.h \
+${RDMACM}/rsocket.h \
+${RDMA}/ib_user_cm.h \
+${RDMA}/ib_user_mad.h \
+${RDMA}/ib_user_sa.h \
+${RDMA}/ib_user_verbs.h	\
+${RDMA}/rdma_user_cm.h \
+${RDMA}/mlx4-abi.h \
+${RDMA}/mlx5-abi.h
+RDMAINCSDIR=	${INCLUDEDIR}/rdma
+
+COMPINCS= \
+${OSM}/complib/cl_atomic.h \
+${OSM}/complib/cl_atomic_osd.h \
+${OSM}/complib/cl_byteswap.h \
+${OSM}/complib/cl_byteswap_osd.h \
+${OSM}/complib/cl_comppool.h \
+${OSM}/complib/cl_debug.h \
+${OSM}/complib/cl_debug_osd.h \
+${OSM}/complib/cl_dispatcher.h \
+${OSM}/complib/cl_event.h \
+${OSM}/complib/cl_event_osd.h \
+${OSM}/complib/cl_event_wheel.h \
+${OSM}/complib/cl_fleximap.h \
+${OSM}/complib/cl_list.h \
+${OSM}/complib/cl_log.h \
+${OSM}/complib/cl_map.h \
+${OSM}/complib/cl_math.h \
+${OSM}/complib/cl_nodenamemap.h \
+${OSM}/complib/cl_packoff.h \
+${OSM}/complib/cl_packon.h \
+${OSM}/complib/cl_passivelock.h \
+${OSM}/complib/cl_pool.h \
+${OSM}/complib/cl_ptr_vector.h \
+${OSM}/complib/cl_qcomppool.h \
+${OSM}/complib/cl_qlist.h \
+${OSM}/complib/cl_qmap.h \
+${OSM}/complib/cl_qpool.h \
+${OSM}/complib/cl_spinlock.h \
+${OSM}/complib/cl_spinlock_osd.h \
+${OSM}/complib/cl_thread.h \
+${OSM}/complib/cl_thread_osd.h \
+${OSM}/complib/cl_threadpool.h \
+${OSM}/complib/cl_timer.h \
+${OSM}/complib/cl_timer_osd.h \
+${OSM}/complib/cl_types.h \
+${OSM}/complib/cl_types_osd.h \
+${OSM}/complib/cl_vector.h
+COMPINCSDIR=	${INCLUDEDIR}/infiniband/complib
+
+OSMINCS= \
+${OSM}/opensm/osm_attrib_req.h \
+${OSM}/opensm/osm_base.h \
+${OSM}/opensm/osm_config.h \
+${OSM}/opensm/osm_congestion_control.h \
+${OSM}/opensm/osm_console.h \
+${OSM}/opensm/osm_console_io.h \
+${OSM}/opensm/osm_db.h \
+${OSM}/opensm/osm_db_pack.h \
+${OSM}/opensm/osm_errors.h \
+${OSM}/opensm/osm_event_plugin.h \
+${OSM}/opensm/osm_file_ids.h \
+${OSM}/opensm/osm_guid.h \
+${OSM}/opensm/osm_helper.h \
+${OSM}/opensm/osm_inform.h \
+${OSM}/opensm/osm_lid_mgr.h \
+${OSM}/opensm/osm_log.h \
+${OSM}/opensm/osm_mad_pool.h \
+${OSM}/opensm/osm_madw.h \
+${OSM}/opensm/osm_mcast_mgr.h \
+${OSM}/opensm/osm_mcast_tbl.h \
+${OSM}/opensm/osm_mcm_port.h \
+${OSM}/opensm/osm_mesh.h \
+${OSM}/opensm/osm_msgdef.h \
+${OSM}/opensm/osm_mtree.h \
+${OSM}/opensm/osm_multicast.h \
+${OSM}/opensm/osm_node.h \
+${OSM}/opensm/osm_opensm.h \
+${OSM}/opensm/osm_partition.h \
+${OSM}/opensm/osm_path.h \
+${OSM}/opensm/osm_perfmgr.h \
+${OSM}/opensm/osm_perfmgr_db.h \
+${OSM}/opensm/osm_pkey.h \
+${OSM}/opensm/osm_port.h \
+${OSM}/opensm/osm_port_profile.h \
+${OSM}/opensm/osm_prefix_route.h \
+${OSM}/opensm/osm_qos_policy.h \
+${OSM}/opensm/osm_remote_sm.h \
+${OSM}/opensm/osm_router.h \
+${OSM}/opensm/osm_sa.h \
+${OSM}/opensm/osm_sa_mad_ctrl.h \
+${OSM}/opensm/osm_service.h \
+${OSM}/opensm/osm_sm.h \
+${OSM}/opensm/osm_sm_mad_ctrl.h \
+${OSM}/opensm/osm_stats.h \
+${OSM}/opensm/osm_subnet.h \
+${OSM}/opensm/osm_switch.h \
+${OSM}/opensm/osm_ucast_cache.h \
+${OSM}/opensm/osm_ucast_lash.h \
+${OSM}/opensm/osm_ucast_mgr.h \
+${OSM}/opensm/osm_version.h \
+${OSM}/opensm/osm_vl15intf.h \
+${OSM}/opensm/st.h
+OSMINCSDIR=	${INCLUDEDIR}/infiniband/opensm
+
+IBAINCS= \
+${OSM}/iba/ib_cm_types.h \
+${OSM}/iba/ib_types.h
+IBAINCSDIR=	${INCLUDEDIR}/infiniband/iba
+
+VENDORINCS= \
+${OSM}/vendor/osm_mtl_bind.h \
+${OSM}/vendor/osm_pkt_randomizer.h \
+${OSM}/vendor/osm_ts_useraccess.h \
+${OSM}/vendor/osm_umadt.h \
+${OSM}/vendor/osm_vendor.h \
+${OSM}/vendor/osm_vendor_al.h \
+${OSM}/vendor/osm_vendor_api.h \
+${OSM}/vendor/osm_vendor_ibumad.h \
+${OSM}/vendor/osm_vendor_mlx.h \
+${OSM}/vendor/osm_vendor_mlx_defs.h \
+${OSM}/vendor/osm_vendor_mlx_dispatcher.h \
+${OSM}/vendor/osm_vendor_mlx_hca.h \
+${OSM}/vendor/osm_vendor_mlx_inout.h \
+${OSM}/vendor/osm_vendor_mlx_rmpp_ctx.h \
+${OSM}/vendor/osm_vendor_mlx_sar.h \
+${OSM}/vendor/osm_vendor_mlx_sender.h \
+${OSM}/vendor/osm_vendor_mlx_svc.h \
+${OSM}/vendor/osm_vendor_mlx_transport.h \
+${OSM}/vendor/osm_vendor_mlx_transport_anafa.h \
+${OSM}/vendor/osm_vendor_mlx_txn.h \
+${OSM}/vendor/osm_vendor_mtl.h \
+${OSM}/vendor/osm_vendor_mtl_hca_guid.h \
+${OSM}/vendor/osm_vendor_mtl_transaction_mgr.h \
+${OSM}/vendor/osm_vendor_sa_api.h \
+${OSM}/vendor/osm_vendor_test.h \
+${OSM}/vendor/osm_vendor_ts.h \
+${OSM}/vendor/osm_vendor_umadt.h
+VENDORINCSDIR=	${INCLUDEDIR}/infiniband/vendor
+
+INCSGROUPS= \
+IBINCS \
+RDMAINCS \
+COMPINCS \
+OSMINCS \
+IBAINCS \
+VENDORINCS
+
+.include <bsd.prog.mk>
diff --git a/contrib/ofed/include/infiniband/byteorder.h b/contrib/ofed/include/byteorder.h
index a7326e49234f..a7326e49234f 100644
--- a/contrib/ofed/include/infiniband/byteorder.h
+++ b/contrib/ofed/include/byteorder.h
diff --git a/contrib/ofed/include/infiniband/byteswap.h b/contrib/ofed/include/byteswap.h
index 29f10049b9e5..29f10049b9e5 100644
--- a/contrib/ofed/include/infiniband/byteswap.h
+++ b/contrib/ofed/include/byteswap.h
diff --git a/contrib/ofed/include/infiniband/endian.h b/contrib/ofed/include/endian.h
index dd1acdc01815..dd1acdc01815 100644
--- a/contrib/ofed/include/infiniband/endian.h
+++ b/contrib/ofed/include/endian.h
diff --git a/contrib/ofed/include/infiniband/Makefile b/contrib/ofed/include/infiniband/Makefile
deleted file mode 100644
index 5d48013b3e9b..000000000000
--- a/contrib/ofed/include/infiniband/Makefile
+++ /dev/null
@@ -1,107 +0,0 @@
-.include <bsd.own.mk>
-
-INCS=
-IBINCS=		byteorder.h byteswap.h endian.h types.h
-IBINCSDIR=	${INCLUDEDIR}/infiniband
-
-IBVERBS=	${.CURDIR}/../../libibverbs/include/infiniband
-VERBINCS=	${IBVERBS}/arch.h ${IBVERBS}/driver.h ${IBVERBS}/kern-abi.h
-VERBINCS+=	${IBVERBS}/marshall.h ${IBVERBS}/opcode.h
-VERBINCS+=	${IBVERBS}/sa-kern-abi.h ${IBVERBS}/sa.h ${IBVERBS}/verbs.h
-VERBINCSDIR=	${INCLUDEDIR}/infiniband
-
-IBCOMMON=	${.CURDIR}/../../management/libibcommon/include/infiniband
-COMMONINCS=	${IBCOMMON}/common.h
-COMMONINCSDIR=	${INCLUDEDIR}/infiniband
-
-IBMAD=		${.CURDIR}/../../management/libibmad/include/infiniband
-MADINCS=	${IBMAD}/mad.h
-MADINCSDIR=	${INCLUDEDIR}/infiniband
-
-IBUMAD=		${.CURDIR}/../../management/libibumad/include/infiniband
-UMADINCS=	${IBUMAD}/umad.h
-UMADINCSDIR=	${INCLUDEDIR}/infiniband
-
-COMPLIB=	${.CURDIR}/../../management/opensm/include/complib
-COMPLIBINCS=	${COMPLIB}/cl_atomic.h ${COMPLIB}/cl_atomic_osd.h
-COMPLIBINCS+= 	${COMPLIB}/cl_byteswap.h ${COMPLIB}/cl_byteswap_osd.h
-COMPLIBINCS+= 	${COMPLIB}/cl_comppool.h ${COMPLIB}/cl_debug.h
-COMPLIBINCS+=	${COMPLIB}/cl_debug_osd.h ${COMPLIB}/cl_dispatcher.h
-COMPLIBINCS+=	${COMPLIB}/cl_event.h ${COMPLIB}/cl_event_osd.h
-COMPLIBINCS+=	${COMPLIB}/cl_event_wheel.h ${COMPLIB}/cl_fleximap.h
-COMPLIBINCS+=	${COMPLIB}/cl_list.h ${COMPLIB}/cl_log.h
-COMPLIBINCS+=	${COMPLIB}/cl_map.h ${COMPLIB}/cl_math.h
-COMPLIBINCS+=	${COMPLIB}/cl_nodenamemap.h ${COMPLIB}/cl_packoff.h
-COMPLIBINCS+=	${COMPLIB}/cl_packon.h ${COMPLIB}/cl_passivelock.h
-COMPLIBINCS+=	${COMPLIB}/cl_pool.h ${COMPLIB}/cl_ptr_vector.h
-COMPLIBINCS+=	${COMPLIB}/cl_qcomppool.h ${COMPLIB}/cl_qlist.h
-COMPLIBINCS+=	${COMPLIB}/cl_qmap.h ${COMPLIB}/cl_qpool.h
-COMPLIBINCS+=	${COMPLIB}/cl_spinlock.h ${COMPLIB}/cl_spinlock_osd.h
-COMPLIBINCS+=	${COMPLIB}/cl_thread.h ${COMPLIB}/cl_thread_osd.h
-COMPLIBINCS+=	${COMPLIB}/cl_threadpool.h ${COMPLIB}/cl_timer.h
-COMPLIBINCS+=	${COMPLIB}/cl_timer_osd.h ${COMPLIB}/cl_types.h
-COMPLIBINCS+=	${COMPLIB}/cl_types_osd.h ${COMPLIB}/cl_vector.h
-COMPLIBINCSDIR=	${INCLUDEDIR}/infiniband/complib
-
-IBADIR=		${.CURDIR}/../../management/opensm/include/iba
-IBAINCS=	${IBADIR}/ib_cm_types.h ${IBADIR}/ib_types.h
-IBAINCSDIR=	${INCLUDEDIR}/infiniband/iba
-
-OPENSM=		${.CURDIR}/../../management/opensm/include/opensm
-
-OPENSMINCS=	${OPENSM}/osm_attrib_req.h ${OPENSM}/osm_base.h
-OPENSMINCS+=	${OPENSM}/osm_config.h ${OPENSM}/osm_console.h
-OPENSMINCS+=	${OPENSM}/osm_console_io.h ${OPENSM}/osm_db.h
-OPENSMINCS+=	${OPENSM}/osm_db_pack.h ${OPENSM}/osm_errors.h
-OPENSMINCS+=	${OPENSM}/osm_event_plugin.h ${OPENSM}/osm_helper.h
-OPENSMINCS+=	${OPENSM}/osm_inform.h ${OPENSM}/osm_lid_mgr.h
-OPENSMINCS+=	${OPENSM}/osm_log.h ${OPENSM}/osm_mad_pool.h
-OPENSMINCS+=	${OPENSM}/osm_madw.h ${OPENSM}/osm_mcast_tbl.h
-OPENSMINCS+=	${OPENSM}/osm_mcm_info.h ${OPENSM}/osm_mcm_port.h
-OPENSMINCS+=	${OPENSM}/osm_msgdef.h ${OPENSM}/osm_mtree.h
-OPENSMINCS+=	${OPENSM}/osm_multicast.h ${OPENSM}/osm_node.h
-OPENSMINCS+=	${OPENSM}/osm_opensm.h ${OPENSM}/osm_partition.h
-OPENSMINCS+=	${OPENSM}/osm_path.h ${OPENSM}/osm_perfmgr.h
-OPENSMINCS+=	${OPENSM}/osm_perfmgr_db.h ${OPENSM}/osm_pkey.h
-OPENSMINCS+=	${OPENSM}/osm_pkey_mgr.h ${OPENSM}/osm_port.h
-OPENSMINCS+=	${OPENSM}/osm_port_profile.h ${OPENSM}/osm_prefix_route.h
-OPENSMINCS+=	${OPENSM}/osm_qos_policy.h ${OPENSM}/osm_remote_sm.h
-OPENSMINCS+=	${OPENSM}/osm_router.h ${OPENSM}/osm_sa.h
-OPENSMINCS+=	${OPENSM}/osm_sa_mad_ctrl.h ${OPENSM}/osm_service.h
-OPENSMINCS+=	${OPENSM}/osm_sm.h ${OPENSM}/osm_sm_mad_ctrl.h
-OPENSMINCS+=	${OPENSM}/osm_stats.h ${OPENSM}/osm_subnet.h
-OPENSMINCS+=	${OPENSM}/osm_switch.h ${OPENSM}/osm_ucast_cache.h
-OPENSMINCS+=	${OPENSM}/osm_ucast_mgr.h ${OPENSM}/osm_version.h
-OPENSMINCS+=	${OPENSM}/osm_vl15intf.h ${OPENSM}/st.h
-OPENSMINCSDIR=	${INCLUDEDIR}/infiniband/opensm
-
-VENDOR=		${.CURDIR}/../../management/opensm/include/vendor
-VENDORINCS=	${VENDOR}/osm_mtl_bind.h ${VENDOR}/osm_pkt_randomizer.h
-VENDORINCS+=	${VENDOR}/osm_ts_useraccess.h ${VENDOR}/osm_umadt.h
-VENDORINCS+=	${VENDOR}/osm_vendor.h ${VENDOR}/osm_vendor_al.h
-VENDORINCS+=	${VENDOR}/osm_vendor_api.h ${VENDOR}/osm_vendor_ibumad.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx.h ${VENDOR}/osm_vendor_mlx_defs.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_dispatcher.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_hca.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_inout.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_rmpp_ctx.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_sar.h ${VENDOR}/osm_vendor_mlx_sender.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_svc.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_transport.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_transport_anafa.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mlx_txn.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mtl.h ${VENDOR}/osm_vendor_mtl_hca_guid.h
-VENDORINCS+=	${VENDOR}/osm_vendor_mtl_transaction_mgr.h
-VENDORINCS+=	${VENDOR}/osm_vendor_sa_api.h
-VENDORINCS+=	${VENDOR}/osm_vendor_test.h ${VENDOR}/osm_vendor_ts.h
-VENDORINCS+=	${VENDOR}/osm_vendor_umadt.h
-VENDORINCSDIR=	${INCLUDEDIR}/infiniband/vendor
-
-IBCM=		${.CURDIR}/../../libibcm/include/infiniband
-IBCMINCS=	${IBCM}/cm.h ${IBCM}/cm_abi.h
-IBCMINCSDIR=	${INCLUDEDIR}/infiniband
-
-INCSGROUPS=	INCS VERBINCS COMMONINCS MADINCS UMADINCS COMPLIBINCS IBAINCS
-INCSGROUPS+=	OPENSMINCS VENDORINCS IBCMINCS IBINCS
-
-.include <bsd.prog.mk>
diff --git a/contrib/ofed/include/rdma/Makefile b/contrib/ofed/include/rdma/Makefile
deleted file mode 100644
index 366790f15c76..000000000000
--- a/contrib/ofed/include/rdma/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-.include <bsd.own.mk>
-
-INCS=
-RDMACM=		${.CURDIR}/../../librdmacm/include/rdma
-RDMACMINCS=	${RDMACM}/rdma_cma.h ${RDMACM}/rdma_cma_abi.h
-RDMACMINCSDIR=	${INCLUDEDIR}/rdma
-
-INCSGROUPS=	RDMACMINCS
-
-.include <bsd.prog.mk>
diff --git a/contrib/ofed/include/infiniband/types.h b/contrib/ofed/include/types.h
index ae60fa374f92..ae60fa374f92 100644
--- a/contrib/ofed/include/infiniband/types.h
+++ b/contrib/ofed/include/types.h
diff --git a/contrib/ofed/include/udma_barrier.h b/contrib/ofed/include/udma_barrier.h
new file mode 100644
index 000000000000..23acf233d763
--- /dev/null
+++ b/contrib/ofed/include/udma_barrier.h
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __UTIL_UDMA_BARRIER_H
+#define __UTIL_UDMA_BARRIER_H
+
+#include <pthread.h>
+
+/* Barriers for DMA.
+
+   These barriers are expliclty only for use with user DMA operations. If you
+   are looking for barriers to use with cache-coherent multi-threaded
+   consitency then look in stdatomic.h. If you need both kinds of synchronicity
+   for the same address then use an atomic operation followed by one
+   of these barriers.
+
+   When reasoning about these barriers there are two objects:
+     - CPU attached address space (the CPU memory could be a range of things:
+       cached/uncached/non-temporal CPU DRAM, uncached MMIO space in another
+       device, pMEM). Generally speaking the ordering is only relative
+       to the local CPU's view of the system. Eg if the local CPU
+       is not guaranteed to see a write from another CPU then it is also
+       OK for the DMA device to also not see the write after the barrier.
+     - A DMA initiator on a bus. For instance a PCI-E device issuing
+       MemRd/MemWr TLPs.
+
+   The ordering guarantee is always stated between those two streams. Eg what
+   happens if a MemRd TLP is sent in via PCI-E relative to a CPU WRITE to the
+   same memory location.
+
+   The providers have a very regular and predictable use of these barriers,
+   to make things very clear each narrow use is given a name and the proper
+   name should be used in the provider as a form of documentation.
+*/
+
+/* Ensure that the device's view of memory matches the CPU's view of memory.
+   This should be placed before any MMIO store that could trigger the device
+   to begin doing DMA, such as a device doorbell ring.
+
+   eg
+    *dma_buf = 1;
+    udma_to_device_barrier();
+    mmio_write(DO_DMA_REG, dma_buf);
+   Must ensure that the device sees the '1'.
+
+   This is required to fence writes created by the libibverbs user. Those
+   writes could be to any CPU mapped memory object with any cachability mode.
+
+   NOTE: x86 has historically used a weaker semantic for this barrier, and
+   only fenced normal stores to normal memory. libibverbs users using other
+   memory types or non-temporal stores are required to use SFENCE in their own
+   code prior to calling verbs to start a DMA.
+*/
+#if defined(__i386__)
+#define udma_to_device_barrier() asm volatile("" ::: "memory")
+#elif defined(__x86_64__)
+#define udma_to_device_barrier() asm volatile("" ::: "memory")
+#elif defined(__PPC64__)
+#define udma_to_device_barrier() asm volatile("sync" ::: "memory")
+#elif defined(__PPC__)
+#define udma_to_device_barrier() asm volatile("sync" ::: "memory")
+#elif defined(__ia64__)
+#define udma_to_device_barrier() asm volatile("mf" ::: "memory")
+#elif defined(__sparc_v9__)
+#define udma_to_device_barrier() asm volatile("membar #StoreStore" ::: "memory")
+#elif defined(__aarch64__)
+#define udma_to_device_barrier() asm volatile("dsb st" ::: "memory");
+#elif defined(__sparc__) || defined(__s390x__)
+#define udma_to_device_barrier() asm volatile("" ::: "memory")
+#else
+#error No architecture specific memory barrier defines found!
+#endif
+
+/* Ensure that all ordered stores from the device are observable from the
+   CPU. This only makes sense after something that observes an ordered store
+   from the device - eg by reading a MMIO register or seeing that CPU memory is
+   updated.
+
+   This guarantees that all reads that follow the barrier see the ordered
+   stores that preceded the observation.
+
+   For instance, this would be used after testing a valid bit in a memory
+   that is a DMA target, to ensure that the following reads see the
+   data written before the MemWr TLP that set the valid bit.
+*/
+#if defined(__i386__)
+#define udma_from_device_barrier() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
+#elif defined(__x86_64__)
+#define udma_from_device_barrier() asm volatile("lfence" ::: "memory")
+#elif defined(__PPC64__)
+#define udma_from_device_barrier() asm volatile("lwsync" ::: "memory")
+#elif defined(__PPC__)
+#define udma_from_device_barrier() asm volatile("sync" ::: "memory")
+#elif defined(__ia64__)
+#define udma_from_device_barrier() asm volatile("mf" ::: "memory")
+#elif defined(__sparc_v9__)
+#define udma_from_device_barrier() asm volatile("membar #LoadLoad" ::: "memory")
+#elif defined(__aarch64__)
+#define udma_from_device_barrier() asm volatile("dsb ld" ::: "memory");
+#elif defined(__sparc__) || defined(__s390x__)
+#define udma_from_device_barrier() asm volatile("" ::: "memory")
+#else
+#error No architecture specific memory barrier defines found!
+#endif
+
+/* Order writes to CPU memory so that a DMA device cannot view writes after
+   the barrier without also seeing all writes before the barrier. This does
+   not guarantee any writes are visible to DMA.
+
+   This would be used in cases where a DMA buffer might have a valid bit and
+   data, this barrier is placed after writing the data but before writing the
+   valid bit to ensure the DMA device cannot observe a set valid bit with
+   unwritten data.
+
+   Compared to udma_to_device_barrier() this barrier is not required to fence
+   anything but normal stores to normal malloc memory. Usage should be:
+
+   write_wqe
+      udma_to_device_barrier();    // Get user memory ready for DMA
+      wqe->addr = ...;
+      wqe->flags = ...;
+      udma_ordering_write_barrier();  // Guarantee WQE written in order
+      wqe->valid = 1;
+*/
+#define udma_ordering_write_barrier() udma_to_device_barrier()
+
+/* Promptly flush writes to MMIO Write Cominbing memory.
+   This should be used after a write to WC memory. This is both a barrier
+   and a hint to the CPU to flush any buffers to reduce latency to TLP
+   generation.
+
+   This is not required to have any effect on CPU memory.
+
+   If done while holding a lock then the ordering of MMIO writes across CPUs
+   must be guaranteed to follow the natural ordering implied by the lock.
+
+   This must also act as a barrier that prevents write combining, eg
+     *wc_mem = 1;
+     mmio_flush_writes();
+     *wc_mem = 2;
+   Must always produce two MemWr TLPs, '1' and '2'. Without the barrier
+   the CPU is allowed to produce a single TLP '2'.
+
+   Note that there is no order guarantee for writes to WC memory without
+   barriers.
+
+   This is intended to be used in conjunction with WC memory to generate large
+   PCI-E MemWr TLPs from the CPU.
+*/
+#if defined(__i386__)
+#define mmio_flush_writes() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
+#elif defined(__x86_64__)
+#define mmio_flush_writes() asm volatile("sfence" ::: "memory")
+#elif defined(__PPC64__)
+#define mmio_flush_writes() asm volatile("sync" ::: "memory")
+#elif defined(__PPC__)
+#define mmio_flush_writes() asm volatile("sync" ::: "memory")
+#elif defined(__ia64__)
+#define mmio_flush_writes() asm volatile("fwb" ::: "memory")
+#elif defined(__sparc_v9__)
+#define mmio_flush_writes() asm volatile("membar #StoreStore" ::: "memory")
+#elif defined(__aarch64__)
+#define mmio_flush_writes() asm volatile("dsb st" ::: "memory");
+#elif defined(__sparc__) || defined(__s390x__)
+#define mmio_flush_writes() asm volatile("" ::: "memory")
+#else
+#error No architecture specific memory barrier defines found!
+#endif
+
+/* Prevent WC writes from being re-ordered relative to other MMIO
+   writes. This should be used before a write to WC memory.
+
+   This must act as a barrier to prevent write re-ordering from different
+   memory types:
+     *mmio_mem = 1;
+     mmio_flush_writes();
+     *wc_mem = 2;
+   Must always produce a TLP '1' followed by '2'.
+
+   This barrier implies udma_to_device_barrier()
+
+   This is intended to be used in conjunction with WC memory to generate large
+   PCI-E MemWr TLPs from the CPU.
+*/
+#define mmio_wc_start() mmio_flush_writes()
+
+/* Keep MMIO writes in order.
+   Currently we lack writel macros that universally guarantee MMIO
+   writes happen in order, like the kernel does. Even worse many
+   providers haphazardly open code writes to MMIO memory omitting even
+   volatile.
+
+   Until this can be fixed with a proper writel macro, this barrier
+   is a stand in to indicate places where MMIO writes should be switched
+   to some future writel.
+*/
+#define mmio_ordered_writes_hack() mmio_flush_writes()
+
+/* Write Combining Spinlock primitive
+
+   Any access to a multi-value WC region must ensure that multiple cpus do not
+   write to the same values concurrently, these macros make that
+   straightforward and efficient if the choosen exclusion is a spinlock.
+
+   The spinlock guarantees that the WC writes issued within the critical
+   section are made visible as TLP to the device. The TLP must be seen by the
+   device strictly in the order that the spinlocks are acquired, and combining
+   WC writes between different sections is not permitted.
+
+   Use of these macros allow the fencing inside the spinlock to be combined
+   with the fencing required for DMA.
+ */
+static inline void mmio_wc_spinlock(pthread_spinlock_t *lock)
+{
+	pthread_spin_lock(lock);
+#if !defined(__i386__) && !defined(__x86_64__)
+	/* For x86 the serialization within the spin lock is enough to
+	 * strongly order WC and other memory types. */
+	mmio_wc_start();
+#endif
+}
+
+static inline void mmio_wc_spinunlock(pthread_spinlock_t *lock)
+{
+	/* It is possible that on x86 the atomic in the lock is strong enough
+	 * to force-flush the WC buffers quickly, and this SFENCE can be
+	 * omitted too. */
+	mmio_flush_writes();
+	pthread_spin_unlock(lock);
+}
+
+#endif