diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2016-08-16 21:02:59 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2016-08-16 21:02:59 +0000 |
commit | 3ca95b020283db6244cab92ede73c969253b6a31 (patch) | |
tree | d16e791e58694facd8f68d3e2797a1eaa8018afc /contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td | |
parent | 27067774dce3388702a4cf744d7096c6fb71b688 (diff) | |
parent | c3aee98e721333f265a88d6bf348e6e468f027d4 (diff) | |
download | src-3ca95b020283db6244cab92ede73c969253b6a31.tar.gz src-3ca95b020283db6244cab92ede73c969253b6a31.zip |
Update llvm to release_39 branch r276489, and resolve conflicts.
Notes
Notes:
svn path=/projects/clang390-import/; revision=304240
Diffstat (limited to 'contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td')
-rw-r--r-- | contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 220 |
1 files changed, 107 insertions, 113 deletions
diff --git a/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index eacfcec78bc7..deb4345e2662 100644 --- a/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -65,53 +65,11 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; +def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; -def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>; // Operands -def uimm4_ptr : Operand<iPTR> { - let PrintMethod = "printUnsignedImm8"; -} - -def uimm6_ptr : Operand<iPTR> { - let PrintMethod = "printUnsignedImm8"; -} - -def simm5 : Operand<i32>; - -def vsplat_uimm1 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_uimm2 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_uimm3 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_uimm4 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_uimm5 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_uimm6 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_uimm8 : Operand<vAny> { - let PrintMethod = "printUnsignedImm8"; -} - -def vsplat_simm5 : Operand<vAny>; - -def vsplat_simm10 : Operand<vAny>; - def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; // Pattern fragments @@ -336,15 +294,33 @@ def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", // Any build_vector that is a constant splat with only a consecutive sequence // of left-most bits set. -def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, - "selectVSplatMaskL", - [build_vector, bitconvert]>; +def vsplat_maskl_bits_uimm3 + : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", + [build_vector, bitconvert]>; +def vsplat_maskl_bits_uimm4 + : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", + [build_vector, bitconvert]>; +def vsplat_maskl_bits_uimm5 + : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", + [build_vector, bitconvert]>; +def vsplat_maskl_bits_uimm6 + : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", + [build_vector, bitconvert]>; // Any build_vector that is a constant splat with only a consecutive sequence // of right-most bits set. -def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, - "selectVSplatMaskR", - [build_vector, bitconvert]>; +def vsplat_maskr_bits_uimm3 + : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", + [build_vector, bitconvert]>; +def vsplat_maskr_bits_uimm4 + : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", + [build_vector, bitconvert]>; +def vsplat_maskr_bits_uimm5 + : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", + [build_vector, bitconvert]>; +def vsplat_maskr_bits_uimm6 + : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", + [build_vector, bitconvert]>; // Any build_vector that is a constant splat with a value that equals 1 // FIXME: These should be a ComplexPattern but we can't use them because the @@ -1185,11 +1161,11 @@ class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, } class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, - ComplexPattern Mask, RegisterOperand ROWD, + SplatComplexPattern Mask, RegisterOperand ROWD, RegisterOperand ROWS = ROWD, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); - dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m); + dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); // Note that binsxi and vselect treat the condition operand the opposite // way to each other. @@ -1202,16 +1178,16 @@ class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, } class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, - RegisterOperand ROWD, + SplatComplexPattern ImmOp, RegisterOperand ROWD, RegisterOperand ROWS = ROWD, InstrItinClass itin = NoItinerary> : - MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>; + MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, - RegisterOperand ROWD, + SplatComplexPattern ImmOp, RegisterOperand ROWD, RegisterOperand ROWS = ROWD, InstrItinClass itin = NoItinerary> : - MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>; + MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, SplatComplexPattern SplatImm, @@ -1225,13 +1201,13 @@ class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, } class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, - ValueType VecTy, RegisterOperand ROD, - RegisterOperand ROWS, + ValueType VecTy, Operand ImmOp, ImmLeaf Imm, + RegisterOperand ROD, RegisterOperand ROWS, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROD:$rd); - dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n); + dag InOperandList = (ins ROWS:$ws, ImmOp:$n); string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); - list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))]; + list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; InstrItinClass Itinerary = itin; } @@ -1249,9 +1225,10 @@ class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, } class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, - RegisterClass RCD, RegisterClass RCWS> : - MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n), - [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> { + Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, + RegisterClass RCWS> : + MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), + [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { bit usesCustomInserter = 1; } @@ -1433,23 +1410,22 @@ class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { } class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, - RegisterOperand ROWD, RegisterOperand ROS, + Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, + RegisterOperand ROS, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); - dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n); + dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); - list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, - ROS:$rs, - immZExt6Ptr:$n))]; + list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; InstrItinClass Itinerary = itin; string Constraints = "$wd = $wd_in"; } class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, - RegisterOperand ROWD, RegisterOperand ROFS> : - MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs), - [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, - immZExt6Ptr:$n))]> { + Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, + RegisterOperand ROFS> : + MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), + [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { bit usesCustomInserter = 1; string Constraints = "$wd = $wd_in"; } @@ -1643,10 +1619,10 @@ class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>; -class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>; -class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>; -class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>; -class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>; +class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; +class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; +class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; +class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>; @@ -1657,10 +1633,18 @@ class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>; -class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>; -class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>; -class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>; -class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>; +class BINSRI_B_DESC + : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, + MSA128BOpnd>; +class BINSRI_H_DESC + : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, + MSA128HOpnd>; +class BINSRI_W_DESC + : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, + MSA128WOpnd>; +class BINSRI_D_DESC + : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, + MSA128DOpnd>; class BMNZ_V_DESC { dag OutOperandList = (outs MSA128BOpnd:$wd); @@ -1867,24 +1851,33 @@ class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, vsplati64_uimm5, MSA128DOpnd>; class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, - GPR32Opnd, MSA128BOpnd>; + uimm4_ptr, immZExt4Ptr, GPR32Opnd, + MSA128BOpnd>; class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, - GPR32Opnd, MSA128HOpnd>; + uimm3_ptr, immZExt3Ptr, GPR32Opnd, + MSA128HOpnd>; class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, - GPR32Opnd, MSA128WOpnd>; + uimm2_ptr, immZExt2Ptr, GPR32Opnd, + MSA128WOpnd>; class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, - GPR64Opnd, MSA128DOpnd>; + uimm1_ptr, immZExt1Ptr, GPR64Opnd, + MSA128DOpnd>; class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, - GPR32Opnd, MSA128BOpnd>; + uimm4_ptr, immZExt4Ptr, GPR32Opnd, + MSA128BOpnd>; class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, - GPR32Opnd, MSA128HOpnd>; + uimm3_ptr, immZExt3Ptr, GPR32Opnd, + MSA128HOpnd>; class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, - GPR32Opnd, MSA128WOpnd>; + uimm2_ptr, immZExt2Ptr, GPR32Opnd, + MSA128WOpnd>; -class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32, +class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, + uimm2_ptr, immZExt2Ptr, FGR32, MSA128W>; -class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64, +class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, + uimm1_ptr, immZExt1Ptr, FGR64, MSA128D>; class CTCMSA_DESC { @@ -2249,14 +2242,14 @@ class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; -class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, - MSA128BOpnd, GPR32Opnd>; -class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, - MSA128HOpnd, GPR32Opnd>; -class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, - MSA128WOpnd, GPR32Opnd>; -class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, - MSA128DOpnd, GPR64Opnd>; +class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, + immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; +class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, + immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; +class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, + immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; +class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, + immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; class INSERT_B_VIDX_PSEUDO_DESC : MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; @@ -2268,8 +2261,10 @@ class INSERT_D_VIDX_PSEUDO_DESC : MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, + uimm2, immZExt2Ptr, MSA128WOpnd, FGR32Opnd>; class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, + uimm1, immZExt1Ptr, MSA128DOpnd, FGR64Opnd>; class INSERT_FW_VIDX_PSEUDO_DESC : @@ -2302,7 +2297,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, - Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, + Operand MemOpnd, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addr); @@ -2312,10 +2307,10 @@ class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, string DecoderMethod = "DecodeMSA128Mem"; } -class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>; -class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>; -class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>; -class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>; +class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; +class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, mem_simm10_lsl1>; +class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, mem_simm10_lsl2>; +class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, mem_simm10_lsl3>; class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; @@ -2323,19 +2318,18 @@ class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, - RegisterOperand RORS = RORD, RegisterOperand RORT = RORD, - InstrItinClass itin = NoItinerary > { + InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs RORD:$rd); - dag InOperandList = (ins RORS:$rs, RORT:$rt, uimm2_plus1:$sa); + dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); - list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt, - (shl RORS:$rs, + list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, + (shl RORD:$rs, immZExt2Lsa:$sa)))]; InstrItinClass Itinerary = itin; } -class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>; -class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>; +class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; +class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, MSA128HOpnd>; @@ -2636,7 +2630,7 @@ class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, - Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, + Operand MemOpnd, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); @@ -2646,10 +2640,10 @@ class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, string DecoderMethod = "DecodeMSA128Mem"; } -class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>; -class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>; -class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>; -class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>; +class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; +class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, mem_simm10_lsl1>; +class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, mem_simm10_lsl2>; +class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3>; class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, MSA128BOpnd>; |