diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2015-05-27 20:26:41 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2015-05-27 20:26:41 +0000 |
commit | ff0cc061ecf297f1556e906d229826fd709f37d6 (patch) | |
tree | bd13a22d9db57ccf3eddbc07b32c18109521d050 /contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h | |
parent | e14ba20ace4c6ab45aca5130defd992ab7d6bf5f (diff) | |
parent | 5a5ac124e1efaf208671f01c46edb15f29ed2a0b (diff) | |
download | src-ff0cc061ecf297f1556e906d229826fd709f37d6.tar.gz src-ff0cc061ecf297f1556e906d229826fd709f37d6.zip |
Merge llvm trunk r238337 from ^/vendor/llvm/dist, resolve conflicts, and
preserve our customizations, where necessary.
Notes
Notes:
svn path=/projects/clang-trunk/; revision=283631
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h')
-rw-r--r-- | contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 43 |
1 files changed, 28 insertions, 15 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 6acfbec24709..0239cabe9e52 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -1,3 +1,4 @@ + //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// // // The LLVM Compiler Infrastructure @@ -26,14 +27,15 @@ namespace llvm { struct EVT; - +class HexagonSubtarget; class HexagonInstrInfo : public HexagonGenInstrInfo { virtual void anchor(); const HexagonRegisterInfo RI; const HexagonSubtarget &Subtarget; - typedef unsigned Opcode_t; public: + typedef unsigned Opcode_t; + explicit HexagonInstrInfo(HexagonSubtarget &ST); /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As @@ -102,15 +104,21 @@ public: const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; - MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, + /// expandPostRAPseudo - This function is called for all pseudo instructions + /// that remain after register allocation. Many pseudo instructions are + /// created to help register allocation. This is the place to convert them + /// into real instructions. The target can edit MI in place, or it can insert + /// new instructions and erase MI. The function should return true if + /// anything was changed. + bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; + + MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, + ArrayRef<unsigned> Ops, int FrameIndex) const override; - MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, - MachineInstr* LoadMI) const override { + MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, + ArrayRef<unsigned> Ops, + MachineInstr *LoadMI) const override { return nullptr; } @@ -154,7 +162,7 @@ public: bool isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override; - bool isValidOffset(const int Opcode, const int Offset) const; + bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; bool isMemOp(const MachineInstr *MI) const; bool isSpillPredRegOp(const MachineInstr *MI) const; @@ -178,6 +186,7 @@ public: bool isConditionalStore(const MachineInstr* MI) const; bool isNewValueInst(const MachineInstr* MI) const; bool isNewValue(const MachineInstr* MI) const; + bool isNewValue(Opcode_t Opcode) const; bool isDotNewInst(const MachineInstr* MI) const; int GetDotOldOp(const int opc) const; int GetDotNewOp(const MachineInstr* MI) const; @@ -193,11 +202,13 @@ public: bool isNewValueStore(const MachineInstr* MI) const; bool isNewValueStore(unsigned Opcode) const; bool isNewValueJump(const MachineInstr* MI) const; + bool isNewValueJump(Opcode_t Opcode) const; bool isNewValueJumpCandidate(const MachineInstr *MI) const; void immediateExtend(MachineInstr *MI) const; - bool isConstExtended(MachineInstr *MI) const; + bool isConstExtended(const MachineInstr *MI) const; + unsigned getSize(const MachineInstr *MI) const; int getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const; unsigned getAddrMode(const MachineInstr* MI) const; @@ -209,10 +220,12 @@ public: bool NonExtEquivalentExists (const MachineInstr *MI) const; short getNonExtOpcode(const MachineInstr *MI) const; bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; - bool PredOpcodeHasNot(Opcode_t Opcode) const; - -private: - int getMatchingCondBranchOpcode(int Opc, bool sense) const; + bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const; + bool isEndLoopN(Opcode_t Opcode) const; + bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond, + unsigned &PredReg, unsigned &PredRegPos, + unsigned &PredRegFlags) const; + int getCondOpcode(int Opc, bool sense) const; }; |