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author | Dimitry Andric <dim@FreeBSD.org> | 2017-01-04 22:19:42 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2017-01-04 22:19:42 +0000 |
commit | 8e0f8b8c96c8b0cf053dbf78cba1d534f05c99a2 (patch) | |
tree | 2173cb011a5acb1fa9d98fcd6a549fec31595377 /contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h | |
parent | d8c03e73dcf4987b182e9ba75540b289daaffc06 (diff) | |
parent | 0c75eea8f661a82866688fd1fc4465883c4dd7d5 (diff) | |
download | src-8e0f8b8c96c8b0cf053dbf78cba1d534f05c99a2.tar.gz src-8e0f8b8c96c8b0cf053dbf78cba1d534f05c99a2.zip |
Merge llvm, clang, lld and lldb trunk r291012, and resolve conflicts.
Notes
Notes:
svn path=/projects/clang400-import/; revision=311327
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h')
-rw-r--r-- | contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 2d184d1484e9..2358d4b7e4c0 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -16,9 +16,14 @@ #include "HexagonRegisterInfo.h" #include "MCTargetDesc/HexagonBaseInfo.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" -#include "llvm/Target/TargetFrameLowering.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/Target/TargetInstrInfo.h" +#include <cstdint> +#include <vector> #define GET_INSTRINFO_HEADER #include "HexagonGenInstrInfo.inc" @@ -29,9 +34,10 @@ struct EVT; class HexagonSubtarget; class HexagonInstrInfo : public HexagonGenInstrInfo { - virtual void anchor(); const HexagonRegisterInfo RI; + virtual void anchor(); + public: explicit HexagonInstrInfo(HexagonSubtarget &ST); @@ -260,7 +266,7 @@ public: /// PredCost. unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, - unsigned *PredCost = 0) const override; + unsigned *PredCost = nullptr) const override; /// Create machine specific model for scheduling. DFAPacketizer * @@ -378,7 +384,6 @@ public: bool PredOpcodeHasJMP_c(unsigned Opcode) const; bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; - short getAbsoluteForm(const MachineInstr &MI) const; unsigned getAddrMode(const MachineInstr &MI) const; unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, @@ -421,13 +426,11 @@ public: unsigned getUnits(const MachineInstr &MI) const; unsigned getValidSubTargets(const unsigned Opcode) const; - /// getInstrTimingClassLatency - Compute the instruction latency of a given /// instruction using Timing Class information, if available. unsigned nonDbgBBSize(const MachineBasicBlock *BB) const; unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const; - void immediateExtend(MachineInstr &MI) const; bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock* NewTarget) const; @@ -438,6 +441,6 @@ public: short xformRegToImmOffset(const MachineInstr &MI) const; }; -} +} // end namespace llvm -#endif +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H |