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author | Dimitry Andric <dim@FreeBSD.org> | 2014-11-24 17:02:24 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2014-11-24 17:02:24 +0000 |
commit | 91bc56ed825ba56b3cc264aa5c95ab84f86832ab (patch) | |
tree | 4df130b28021d86e13bf4565ef58c1c5a5e093b4 /contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | |
parent | 9efc7e72bb1daf5d6019871d9c93a1c488a11229 (diff) | |
parent | 5ca98fd98791947eba83a1ed3f2c8191ef7afa6c (diff) | |
download | src-91bc56ed825ba56b3cc264aa5c95ab84f86832ab.tar.gz src-91bc56ed825ba56b3cc264aa5c95ab84f86832ab.zip |
Merge llvm 3.5.0 release from ^/vendor/llvm/dist, resolve conflicts, and
preserve our customizations, where necessary.
Notes
Notes:
svn path=/projects/clang350-import/; revision=274968
Diffstat (limited to 'contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h')
-rw-r--r-- | contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 84 |
1 files changed, 48 insertions, 36 deletions
diff --git a/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h index e28fff68f4e2..833d3f218480 100644 --- a/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -14,7 +14,7 @@ #ifndef ARMBASEREGISTERINFO_H #define ARMBASEREGISTERINFO_H -#include "ARM.h" +#include "MCTargetDesc/ARMBaseInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #define GET_REGINFO_HEADER @@ -42,7 +42,7 @@ static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { case R4: case R5: case R6: case R7: case LR: case SP: case PC: return true; - case R8: case R9: case R10: case R11: + case R8: case R9: case R10: case R11: case R12: // For iOS we want r7 and lr to be next to each other. return !isIOS; default: @@ -53,7 +53,7 @@ static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { using namespace ARM; switch (Reg) { - case R8: case R9: case R10: case R11: + case R8: case R9: case R10: case R11: case R12: // iOS has this second area. return isIOS; default: @@ -100,8 +100,9 @@ protected: public: /// Code Generation virtual methods... - const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; - const uint32_t *getCallPreservedMask(CallingConv::ID) const; + const MCPhysReg * + getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override; + const uint32_t *getCallPreservedMask(CallingConv::ID) const override; const uint32_t *getNoPreservedMask() const; /// getThisReturnPreservedMask - Returns a call preserved mask specific to the @@ -113,48 +114,51 @@ public: /// Should return NULL in the case that the calling convention does not have /// this property const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const; - - BitVector getReservedRegs(const MachineFunction &MF) const; - const TargetRegisterClass* - getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const; - const TargetRegisterClass* - getCrossCopyRegClass(const TargetRegisterClass *RC) const; + BitVector getReservedRegs(const MachineFunction &MF) const override; - const TargetRegisterClass* - getLargestLegalSuperClass(const TargetRegisterClass *RC) const; + const TargetRegisterClass * + getPointerRegClass(const MachineFunction &MF, + unsigned Kind = 0) const override; + const TargetRegisterClass * + getCrossCopyRegClass(const TargetRegisterClass *RC) const override; + + const TargetRegisterClass * + getLargestLegalSuperClass(const TargetRegisterClass *RC) const override; unsigned getRegPressureLimit(const TargetRegisterClass *RC, - MachineFunction &MF) const; + MachineFunction &MF) const override; void getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, - const VirtRegMap *VRM) const; + const VirtRegMap *VRM) const override; void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, - MachineFunction &MF) const; + MachineFunction &MF) const override; - virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const; + bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override; bool hasBasePointer(const MachineFunction &MF) const; bool canRealignStack(const MachineFunction &MF) const; - bool needsStackRealignment(const MachineFunction &MF) const; - int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const; - bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const; + bool needsStackRealignment(const MachineFunction &MF) const override; + int64_t getFrameIndexInstrOffset(const MachineInstr *MI, + int Idx) const override; + bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, - int64_t Offset) const; - void resolveFrameIndex(MachineBasicBlock::iterator I, - unsigned BaseReg, int64_t Offset) const; - bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const; + int64_t Offset) const override; + void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + int64_t Offset) const override; + bool isFrameOffsetLegal(const MachineInstr *MI, + int64_t Offset) const override; bool cannotEliminateFrame(const MachineFunction &MF) const; // Debug information queries. - unsigned getFrameRegister(const MachineFunction &MF) const; + unsigned getFrameRegister(const MachineFunction &MF) const override; unsigned getBaseRegister() const { return BasePtr; } bool isLowRegister(unsigned Reg) const; @@ -164,25 +168,33 @@ public: /// specified immediate. virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - DebugLoc dl, - unsigned DestReg, unsigned SubIdx, - int Val, - ARMCC::CondCodes Pred = ARMCC::AL, + DebugLoc dl, unsigned DestReg, unsigned SubIdx, + int Val, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0, unsigned MIFlags = MachineInstr::NoFlags)const; /// Code Generation virtual methods... - virtual bool requiresRegisterScavenging(const MachineFunction &MF) const; + bool mayOverrideLocalAssignment() const override; + + bool requiresRegisterScavenging(const MachineFunction &MF) const override; + + bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; - virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; + bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; - virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const; + bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; - virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const; + void eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS = nullptr) const override; - virtual void eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, unsigned FIOperandNum, - RegScavenger *RS = NULL) const; + /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true + bool shouldCoalesce(MachineInstr *MI, + const TargetRegisterClass *SrcRC, + unsigned SubReg, + const TargetRegisterClass *DstRC, + unsigned DstSubReg, + const TargetRegisterClass *NewRC) const override; }; } // end namespace llvm |