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| author | Dimitry Andric <dim@FreeBSD.org> | 2022-07-04 19:20:19 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-02-08 19:02:26 +0000 |
| commit | 81ad626541db97eb356e2c1d4a20eb2a26a766ab (patch) | |
| tree | 311b6a8987c32b1e1dcbab65c54cfac3fdb56175 /contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | |
| parent | 5fff09660e06a66bed6482da9c70df328e16bbb6 (diff) | |
| parent | 145449b1e420787bb99721a429341fa6be3adfb6 (diff) | |
| download | src-81ad626541db97eb356e2c1d4a20eb2a26a766ab.tar.gz src-81ad626541db97eb356e2c1d4a20eb2a26a766ab.zip | |
Merge llvm-project main llvmorg-15-init-15358-g53dc0f10787
This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and
openmp to llvmorg-15-init-15358-g53dc0f10787.
PR: 265425
MFC after: 2 weeks
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index c429a9298739..b50927cfcca5 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -24,8 +24,9 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { const RISCVSubtarget *Subtarget = nullptr; public: - explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) - : SelectionDAGISel(TargetMachine) {} + explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, + CodeGenOpt::Level OptLevel) + : SelectionDAGISel(TargetMachine, OptLevel) {} StringRef getPassName() const override { return "RISCV DAG->DAG Pattern Instruction Selection"; @@ -44,8 +45,10 @@ public: bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) override; - bool SelectAddrFI(SDValue Addr, SDValue &Base); + bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset); + bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset); bool SelectBaseAddr(SDValue Addr, SDValue &Base); + bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset); bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt); bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) { @@ -117,12 +120,14 @@ public: private: bool doPeepholeLoadStoreADDI(SDNode *Node); bool doPeepholeSExtW(SDNode *Node); + bool doPeepholeMaskedRVV(SDNode *Node); }; namespace RISCV { struct VLSEGPseudo { uint16_t NF : 4; uint16_t Masked : 1; + uint16_t IsTU : 1; uint16_t Strided : 1; uint16_t FF : 1; uint16_t Log2SEW : 3; @@ -133,6 +138,7 @@ struct VLSEGPseudo { struct VLXSEGPseudo { uint16_t NF : 4; uint16_t Masked : 1; + uint16_t IsTU : 1; uint16_t Ordered : 1; uint16_t Log2SEW : 3; uint16_t LMUL : 3; @@ -187,6 +193,13 @@ struct VLX_VSXPseudo { uint16_t Pseudo; }; +struct RISCVMaskedPseudoInfo { + uint16_t MaskedPseudo; + uint16_t UnmaskedPseudo; + uint16_t UnmaskedTUPseudo; + uint8_t MaskOpIdx; +}; + #define GET_RISCVVSSEGTable_DECL #define GET_RISCVVLSEGTable_DECL #define GET_RISCVVLXSEGTable_DECL @@ -195,6 +208,7 @@ struct VLX_VSXPseudo { #define GET_RISCVVSETable_DECL #define GET_RISCVVLXTable_DECL #define GET_RISCVVSXTable_DECL +#define GET_RISCVMaskedPseudosTable_DECL #include "RISCVGenSearchableTables.inc" } // namespace RISCV |