diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2023-09-02 21:17:18 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2023-12-08 17:34:50 +0000 |
commit | 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e (patch) | |
tree | 62f873df87c7c675557a179e0c4c83fe9f3087bc /contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp | |
parent | cf037972ea8863e2bab7461d77345367d2c1e054 (diff) | |
parent | 7fa27ce4a07f19b07799a767fc29416f3b625afb (diff) | |
download | src-06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e.tar.gz src-06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e.zip |
Merge llvm-project main llvmorg-17-init-19304-gd0b54bb50e51
This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and
openmp to llvm-project main llvmorg-17-init-19304-gd0b54bb50e51, the
last commit before the upstream release/17.x branch was created.
PR: 273753
MFC after: 1 month
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp')
-rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp | 86 |
1 files changed, 59 insertions, 27 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp b/contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp index 00626604d81c..61867d74bfa2 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -119,10 +119,10 @@ public: SmallVector<PHIInfo, 8> PHIs; -private: /// The branch condition determined by analyzeBranch. SmallVector<MachineOperand, 4> Cond; +private: /// Instructions in Head that define values used by the conditional blocks. /// The hoisted instructions must be inserted after these instructions. SmallPtrSet<MachineInstr*, 8> InsertAfter; @@ -263,9 +263,8 @@ bool SSAIfConv::InstrDependenciesAllowIfConv(MachineInstr *I) { // Remember clobbered regunits. if (MO.isDef() && Reg.isPhysical()) - for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid(); - ++Units) - ClobberedRegUnits.set(*Units); + for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) + ClobberedRegUnits.set(Unit); if (!MO.readsReg() || !Reg.isVirtual()) continue; @@ -343,8 +342,11 @@ bool SSAIfConv::canPredicateInstrs(MachineBasicBlock *MBB) { // Apply predicate to all instructions in the machine block. void SSAIfConv::PredicateBlock(MachineBasicBlock *MBB, bool ReversePredicate) { auto Condition = Cond; - if (ReversePredicate) - TII->reverseBranchCondition(Condition); + if (ReversePredicate) { + bool CanRevCond = !TII->reverseBranchCondition(Condition); + assert(CanRevCond && "Reversed predicate is not supported"); + (void)CanRevCond; + } // Terminators don't need to be predicated as they will be removed. for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->getFirstTerminator(); @@ -391,19 +393,17 @@ bool SSAIfConv::findInsertionPoint() { continue; // I clobbers Reg, so it isn't live before I. if (MO.isDef()) - for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid(); - ++Units) - LiveRegUnits.erase(*Units); + for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) + LiveRegUnits.erase(Unit); // Unless I reads Reg. if (MO.readsReg()) Reads.push_back(Reg.asMCReg()); } // Anything read by I is live before I. while (!Reads.empty()) - for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid(); - ++Units) - if (ClobberedRegUnits.test(*Units)) - LiveRegUnits.insert(*Units); + for (MCRegUnit Unit : TRI->regunits(Reads.pop_back_val())) + if (ClobberedRegUnits.test(Unit)) + LiveRegUnits.insert(Unit); // We can't insert before a terminator. if (I != FirstTerm && I->isTerminator()) @@ -760,14 +760,14 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks, namespace { class EarlyIfConverter : public MachineFunctionPass { - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; MCSchedModel SchedModel; - MachineRegisterInfo *MRI; - MachineDominatorTree *DomTree; - MachineLoopInfo *Loops; - MachineTraceMetrics *Traces; - MachineTraceMetrics::Ensemble *MinInstr; + MachineRegisterInfo *MRI = nullptr; + MachineDominatorTree *DomTree = nullptr; + MachineLoopInfo *Loops = nullptr; + MachineTraceMetrics *Traces = nullptr; + MachineTraceMetrics::Ensemble *MinInstr = nullptr; SSAIfConv IfConv; public: @@ -873,8 +873,40 @@ bool EarlyIfConverter::shouldConvertIf() { if (Stress) return true; + // Do not try to if-convert if the condition has a high chance of being + // predictable. + MachineLoop *CurrentLoop = Loops->getLoopFor(IfConv.Head); + // If the condition is in a loop, consider it predictable if the condition + // itself or all its operands are loop-invariant. E.g. this considers a load + // from a loop-invariant address predictable; we were unable to prove that it + // doesn't alias any of the memory-writes in the loop, but it is likely to + // read to same value multiple times. + if (CurrentLoop && any_of(IfConv.Cond, [&](MachineOperand &MO) { + if (!MO.isReg() || !MO.isUse()) + return false; + Register Reg = MO.getReg(); + if (Register::isPhysicalRegister(Reg)) + return false; + + MachineInstr *Def = MRI->getVRegDef(Reg); + return CurrentLoop->isLoopInvariant(*Def) || + all_of(Def->operands(), [&](MachineOperand &Op) { + if (Op.isImm()) + return true; + if (!MO.isReg() || !MO.isUse()) + return false; + Register Reg = MO.getReg(); + if (Register::isPhysicalRegister(Reg)) + return false; + + MachineInstr *Def = MRI->getVRegDef(Reg); + return CurrentLoop->isLoopInvariant(*Def); + }); + })) + return false; + if (!MinInstr) - MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount); + MinInstr = Traces->getEnsemble(MachineTraceStrategy::TS_MinInstrCount); MachineTraceMetrics::Trace TBBTrace = MinInstr->getTrace(IfConv.getTPred()); MachineTraceMetrics::Trace FBBTrace = MinInstr->getTrace(IfConv.getFPred()); @@ -1084,13 +1116,13 @@ bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) { namespace { class EarlyIfPredicator : public MachineFunctionPass { - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; TargetSchedModel SchedModel; - MachineRegisterInfo *MRI; - MachineDominatorTree *DomTree; - MachineBranchProbabilityInfo *MBPI; - MachineLoopInfo *Loops; + MachineRegisterInfo *MRI = nullptr; + MachineDominatorTree *DomTree = nullptr; + MachineBranchProbabilityInfo *MBPI = nullptr; + MachineLoopInfo *Loops = nullptr; SSAIfConv IfConv; public: |