aboutsummaryrefslogtreecommitdiff
path: root/contrib/gcc
diff options
context:
space:
mode:
authorJohn-Mark Gurney <jmg@FreeBSD.org>2013-09-03 17:33:29 +0000
committerJohn-Mark Gurney <jmg@FreeBSD.org>2013-09-03 17:33:29 +0000
commit003f0fa63f779bf3e5c2e43351a5c1dd91a7e627 (patch)
tree3f50e4666b3a9fe46114ce8214d5e64766419e43 /contrib/gcc
parent4b1fb8ff162617839655a2abf755969779c3e697 (diff)
downloadsrc-003f0fa63f779bf3e5c2e43351a5c1dd91a7e627.tar.gz
src-003f0fa63f779bf3e5c2e43351a5c1dd91a7e627.zip
add support to gcc for AES and PCLMUL intrinsics... This addes the
-maes option, but not the -mpclmul option as I ran out of bits in the 32 bit flags field... You can -D__PCLMUL__ to get this, but it won't be compatible w/ clang and modern gcc... Reviewed by: -current, -toolchain
Notes
Notes: svn path=/head/; revision=255185
Diffstat (limited to 'contrib/gcc')
-rw-r--r--contrib/gcc/config/i386/i386.c12
-rw-r--r--contrib/gcc/config/i386/i386.h2
-rw-r--r--contrib/gcc/config/i386/i386.opt4
-rw-r--r--contrib/gcc/doc/invoke.texi12
-rw-r--r--contrib/gcc/opth-gen.awk2
5 files changed, 26 insertions, 6 deletions
diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c
index 0187cb25d0fc..1598ae91ecaa 100644
--- a/contrib/gcc/config/i386/i386.c
+++ b/contrib/gcc/config/i386/i386.c
@@ -1684,6 +1684,14 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
}
return true;
+ case OPT_maes:
+ if (!value)
+ {
+ target_flags &= ~MASK_AES;
+ target_flags_explicit |= MASK_AES;
+ }
+ return true;
+
default:
return true;
}
@@ -2187,6 +2195,10 @@ override_options (void)
if (TARGET_SSE3)
target_flags |= MASK_SSE2;
+ /* Turn on SSE2 builtins for -maes. */
+ if (TARGET_AES)
+ target_flags |= MASK_SSE2;
+
/* Turn on SSE builtins for -msse2. */
if (TARGET_SSE2)
target_flags |= MASK_SSE;
diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h
index e918fc309ca9..1394fbabfa71 100644
--- a/contrib/gcc/config/i386/i386.h
+++ b/contrib/gcc/config/i386/i386.h
@@ -428,6 +428,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
builtin_define ("__SSSE3__"); \
if (TARGET_SSE4A) \
builtin_define ("__SSE4A__"); \
+ if (TARGET_AES) \
+ builtin_define ("__AES__"); \
if (TARGET_SSE_MATH && TARGET_SSE) \
builtin_define ("__SSE_MATH__"); \
if (TARGET_SSE_MATH && TARGET_SSE2) \
diff --git a/contrib/gcc/config/i386/i386.opt b/contrib/gcc/config/i386/i386.opt
index fa73e177e7b2..4de75698f19e 100644
--- a/contrib/gcc/config/i386/i386.opt
+++ b/contrib/gcc/config/i386/i386.opt
@@ -205,6 +205,10 @@ msse4a
Target Report Mask(SSE4A)
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
+maes
+Target Report Mask(AES)
+Support AES built-in functions and code generation.
+
mpopcnt
Target Report Mask(POPCNT)
Support code generation of popcount instruction for popcount built-ins
diff --git a/contrib/gcc/doc/invoke.texi b/contrib/gcc/doc/invoke.texi
index 0f66c3dc28b6..13b9ae93d957 100644
--- a/contrib/gcc/doc/invoke.texi
+++ b/contrib/gcc/doc/invoke.texi
@@ -513,7 +513,7 @@ in the following sections.
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
--mmmx -msse -msse2 -msse3 -mssse3 -msse4a -m3dnow -mpopcnt -mabm @gol
+-mmmx -msse -msse2 -msse3 -mssse3 -msse4a -m3dnow -mpopcnt -mabm -maes @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -msseregparm @gol
@@ -9367,6 +9367,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@itemx -mno-popcnt
@item -mabm
@itemx -mno-abm
+@item -maes
+@itemx -mno-aes
@opindex mmmx
@opindex mno-mmx
@opindex msse
@@ -9374,10 +9376,10 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3, SSE4A, ABM or 3DNow! extended instruction sets.
-These extensions are also available as built-in functions: see
-@ref{X86 Built-in Functions}, for details of the functions enabled and
-disabled by these switches.
+SSE, SSE2, SSE3, SSSE3, SSE4A, ABM, AES or 3DNow! extended
+instruction sets. These extensions are also available as built-in
+functions: see @ref{X86 Built-in Functions}, for details of the functions
+enabled and disabled by these switches.
To have SSE/SSE2 instructions generated automatically from floating-point
code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
diff --git a/contrib/gcc/opth-gen.awk b/contrib/gcc/opth-gen.awk
index e7ffc1a646eb..84b3170935fc 100644
--- a/contrib/gcc/opth-gen.awk
+++ b/contrib/gcc/opth-gen.awk
@@ -87,7 +87,7 @@ for (i = 0; i < n_extra_masks; i++) {
}
for (var in masknum) {
- if (masknum[var] > 31) {
+ if (masknum[var] > 32) {
if (var == "")
print "#error too many target masks"
else