Initial import of GNU binutils version 2.8.1. Believe it or not,

this is heavily stripped down.

7 files changed, 5428 insertions, 0 deletions

diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog
new file mode 100644
index 000000000000..8a1b7d75f2b1
--- /dev/null
+++ b/contrib/binutils/include/opcode/ChangeLog
@@ -0,0 +1,1109 @@
+Mon May 12 16:26:50 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h (movd): only Reg32 is allowed.
+
+	* i386.h: add fcomp and ud2.  From Wayne Scott
+	<wscott@ichips.intel.com>.
+
+Mon May  5 17:16:21 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Add MMX instructions.
+
+Mon May  5 12:45:19 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h: Remove W modifier from conditional move instructions.
+
+Mon Apr 14 14:56:58 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp
+	with no arguments to match that generated by the UnixWare
+	assembler.
+
+Thu Apr 10 14:35:00 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg.
+	(cgen_parse_operand_fn): Declare.
+	(cgen_init_parse_operand): Declare.
+	(cgen_parse_operand): Renamed from cgen_asm_parse_operand,
+	new argument `want'.
+	(enum cgen_parse_operand_result): Renamed from cgen_asm_result.
+	(enum cgen_parse_operand_type): New enum.
+
+Sat Apr  5 13:14:05 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Revert last patch for the NON_BROKEN_OPCODES cases.
+
+Fri Apr  4 11:46:11 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h: New file.
+
+Fri Apr  4 14:02:32 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
+	fdivrp.
+
+Mon Mar 24 14:38:15 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Add iclr.
+
+Thu Mar 20 19:49:10 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Change DW to W for cmpxchg and xadd, since they don't
+	take a direction bit.
+
+Sat Mar 15 19:03:29 1997  H.J. Lu  <hjl@lucon.org>
+
+	* sparc.h (sparc_opcode_lookup_arch): Use full prototype.
+
+Fri Mar 14 15:22:01 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sparc.h: Include <ansidecl.h>.  Update function declarations to
+	use prototypes, and to use const when appropriate.
+
+Thu Mar  6 14:18:30 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_RELAX): Define.
+
+Mon Feb 24 15:15:56 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Change pre_defined_registers to 
+	d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
+
+Sat Feb 22 21:25:00 1997  Dawn Perchik  <dawn@cygnus.com>
+
+	* mips.h: Add macros for cop0, cop1 cop2 and cop3.
+	Change mips_opcodes from const array to a pointer, 
+	and change bfd_mips_num_opcodes from const int to int,
+	so that we can increase the size of the mips opcodes table 
+	dynamically.
+	
+Wed Jan 29 09:37:25 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h (MN10200_OPERAND_RELAX): Define.
+
+Wed Dec 18 10:06:31 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h (MN10200_OPERAND_NOCHECK): Define.
+
+Sat Dec 14 10:48:31 1996  Fred Fish  <fnf@ninemoons.com>
+
+	* mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
+	* mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
+	
+Mon Dec  9 16:45:39 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h: Flesh out structures and definitions needed by
+	the mn10200 assembler & disassembler.
+
+Tue Nov 26 10:46:56 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h: Add mips16 definitions.
+
+Mon Nov 25 17:56:54 1996  J.T. Conklin  <jtc@cygnus.com>
+
+	* m68k.h: Document new <, >, m, n, o and p operand specifiers.
+
+Wed Nov 20 10:59:41 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_PCREL): Define.
+	(MN10300_OPERAND_MEMADDR): Define.
+
+Tue Nov 19 13:30:40 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_REG_LIST): Define.
+
+Wed Nov  6 13:41:08 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_SPLIT): Define.
+
+Tue Nov  5 13:26:12 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_EXTENDED): Define.
+
+Mon Nov  4 12:52:48 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_REPEATED): Define.
+
+Fri Nov  1 10:31:02 1996  Richard Henderson  <rth@tamu.edu>
+
+	* alpha.h: Don't include "bfd.h"; private relocation types are now
+ 	negative to minimize problems with shared libraries.  Organize
+ 	instruction subsets by AMASK extensions and PALcode
+ 	implementation.
+	(struct alpha_operand): Move flags slot for better packing.
+
+Thu Oct 10 14:29:11 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (FMT_*): Move operand format definitions
+	here.
+
+Tue Oct  8 14:48:07 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_PAREN): Define.
+
+Mon Oct  7 16:52:11 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (mn10300_opcode): Add "format" field.
+	(MN10300_OPERAND_*): Define.
+
+Thu Oct  3 10:33:46 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10x00.h: Delete.
+	* mn10200.h, mn10300.h: New files.
+
+Wed Oct  2 21:31:26 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10x00.h: New file.
+
+Fri Sep 13 14:58:13 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (stmac): Add missing instruction.
+
+Fri Aug 16 14:44:15 1996  James G. Smith  <jsmith@cygnus.co.uk>
+
+	* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
+ 	OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
+ 	OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
+ 	OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
+ 	OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
+ 	Defined.
+
+Fri Aug 16 00:15:15 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
+	a 3 bit space id instead of a 2 bit space id.
+
+Thu Aug 15 13:11:46 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Add some additional defines to support the
+ 	assembler in determining which operations can be done in parallel.
+
+Tue Aug  6 11:13:22 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (SN): Define.
+	(eepmov.b): Renamed from "eepmov"
+	(nop, bpt, rte, rts, sleep, clrmac): These have no size associated
+	with them.
+
+Fri Jul 26 11:47:10 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h (OPERAND_SHIFT): New operand flag.
+
+Thu Jul 25 12:06:22 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Changes for divs, parallel-only instructions, and
+ 	signed numbers.
+
+Mon Jul 22 11:21:15 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h (pd_reg): Define. Putting the definition here allows
+	the assembler and disassembler to share the same struct.
+
+Mon Jul 22 12:15:25 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i960.h (i960_opcodes): "halt" takes an argument.  From Stephen
+	Williams <steve@icarus.com>.
+
+Wed Jul 17 14:46:38 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: New file. 
+
+Thu Jul 11 12:09:15 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (band, bclr): Force high bit of immediate nibble to zero.
+
+Wed Jul  3 14:30:12 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+ 	* m68k.h (mcf5200): New macro.
+	Document names of coldfire control registers.
+
+Tue Jul  2 23:05:45 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (SRC_IN_DST): Define.
+
+	* h8300.h (UNOP3): Mark the register operand in this insn
+	as a source operand, not a destination operand.
+	(SHIFT_2, SHIFT_IMM): Remove.  Eliminate all references.
+	(UNOP3): Change SHIFT_IMM to IMM for H8/S bitops.  Mark
+	register operand with SRC_IN_DST.
+
+Fri Jun 21 13:52:17 1996  Richard Henderson  <rth@tamu.edu>
+
+	* alpha.h: New file.
+
+Thu Jun 20 15:02:57 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* rs6k.h: Remove obsolete file.
+
+Wed Jun 19 15:29:38 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
+	fdivp, and fdivrp.  Add ffreep.
+
+Tue Jun 18 16:06:00 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
+
+	* h8300.h: Reorder various #defines for readability.
+	(ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define.
+	(BITOP): Accept additional (unused) argument.  All callers changed.
+	(EBITOP): Likewise.
+	(O_LAST): Bump.
+	(ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
+	
+	* h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
+	(O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
+	(BITOP, EBITOP): Handle new H8/S addressing modes for
+	bit insns.
+	(UNOP3): Handle new shift/rotate insns on the H8/S.
+	(insns using exr): New instructions.
+	(tas, mac, ldmac, clrmac, ldm, stm): New instructions.
+	
+Thu May 23 16:56:48 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (add.l): Undo Apr 5th change.  The manual I had
+	was incorrect.
+
+Mon May  6 23:38:22 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (START): Remove.
+	(MEMRELAX): Define.  Mark absolute memory operands in mov.b, mov.w
+	and mov.l insns that can be relaxed.
+
+Tue Apr 30 18:30:58 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Remove Abs32 from lcall.
+
+Mon Apr 22 17:09:23 1996  Doug Evans  <dje@blues.cygnus.com>
+
+	* sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro.
+	(SLCPOP): New macro.
+	Mark X,Y opcode letters as in use.
+
+Thu Apr 11 17:28:18 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sparc.h (F_FLOAT, F_FBR): Define.
+
+Fri Apr  5 16:55:34 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (ABS8MEM): Renamed from ABSMOV.  Remove ABSMOV
+	from all insns.
+	(ABS8SRC,ABS8DST): Add ABS8MEM.
+	(add.l): Fix reg+reg variant.
+	(eepmov.w): Renamed from eepmovw.
+	(ldc,stc): Fix many cases.
+
+Sun Mar 31 13:30:03 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
+
+Thu Mar  7 15:08:23 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (O): Mark operand letter as in use.
+
+Tue Feb 20 20:46:21 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
+	Mark operand letters uU as in use.
+
+Mon Feb 19 01:59:08 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET.
+	(sparc_opcode_arch): Delete member `conflicts'.  Add `supported'.
+	(SPARC_OPCODE_SUPPORTED): New macro.
+	(SPARC_OPCODE_CONFLICT_P): Rewrite.
+	(F_NOTV9): Delete.
+
+Fri Feb 16 12:23:34 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* sparc.h (sparc_opcode_lookup_arch) Make return type in
+	declaration consistent with return type in definition.
+
+Wed Feb 14 18:14:11 1996  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Remove Data32 from pushf and popf.
+
+Thu Feb  8 14:27:21 1996  James Carlson <carlson@xylogics.com>
+
+	* i386.h (i386_regtab): Add 80486 test registers.
+
+Mon Feb  5 18:35:46 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i960.h (I_HX): Define.
+	(i960_opcodes): Add HX instruction.
+
+Mon Jan 29 12:43:39 1996  Ken Raeburn  <raeburn@cygnus.com>
+
+	* i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw,
+	and fclex.
+
+Wed Jan 24 22:36:59 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture.
+	(SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P.
+	(bfd_* defines): Delete.
+	(sparc_opcode_archs): Replaces architecture_pname.
+	(sparc_opcode_lookup_arch): Declare.
+	(NUMOPCODES): Delete.
+
+Mon Jan 22 08:24:32 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (enum sparc_architecture): Add v9a.
+	(ARCHITECTURES_CONFLICT_P): Update.
+
+Thu Dec 28 13:27:53 1995  John Hassey  <hassey@rtp.dg.com>
+
+	* i386.h: Added Pentium Pro instructions.
+
+Thu Nov  2 22:59:22 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Document new 'W' operand place.
+
+Tue Oct 24 10:49:10 1995  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Add lci and syncdma instructions.
+
+Mon Oct 23 11:09:16 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
+
+	* mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
+ 	instructions.
+
+Mon Oct 16 10:28:15 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for
+	assembler's -mcom and -many switches.
+
+Wed Oct 11 16:56:33 1995  Ken Raeburn  <raeburn@cygnus.com>
+
+	* i386.h: Fix cmpxchg8b extension opcode description.
+
+Thu Oct  5 18:03:36 1995  Ken Raeburn  <raeburn@cygnus.com>
+
+	* i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b,
+	and register cr4.
+
+Tue Sep 19 15:26:43 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Change comment: split type P into types 0, 1 and 2.
+
+Wed Aug 30 13:50:55 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_{encode,decode}_prefetch): Declare.
+
+Tue Aug 29 15:34:58 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
+
+Wed Aug  2 18:32:19 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68kmri.h: Remove.
+
+	* m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the
+	declarations.  Remove F_ALIAS and flag field of struct
+	m68k_opcode.  Change arch field of struct m68k_opcode to unsigned
+	int.  Make name and args fields of struct m68k_opcode const.
+
+Wed Aug  2 08:16:46 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (F_NOTV9): Define.
+
+Tue Jul 11 14:20:42 1995  Jeff Spiegel  <jeffs@lsil.com>
+
+	* mips.h (INSN_4010): Define.
+
+Wed Jun 21 18:49:51 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* m68k.h (TBL1): Reverse sense of "round" argument in result.
+
+	Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>:
+	* m68k.h: Fix argument descriptions of coprocessor
+	instructions to allow only alterable operands where appropriate.
+	[!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
+	(m68k_opcode_aliases): Add more aliases.
+
+
+Fri Apr 14 22:15:34 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* m68k.h: Added explcitly short-sized conditional branches, and a
+	bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
+	svr4-based configurations.
+
+
+Mon Mar 13 21:30:01 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	Mon Feb 27 08:36:39 1995  Bryan Ford  <baford@cs.utah.edu>
+	* i386.h: added missing Data16/Data32 flags to a few instructions.
+
+Wed Mar  8 15:19:53 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (OP_MASK_FR, OP_SH_FR): Define.
+	(OP_MASK_BCC, OP_SH_BCC): Define.
+	(OP_MASK_PREFX, OP_SH_PREFX): Define.
+	(OP_MASK_CCC, OP_SH_CCC): Define.
+	(INSN_READ_FPR_R): Define.
+	(INSN_RFE): Delete.
+
+Wed Mar  8 03:13:23 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* m68k.h (enum m68k_architecture): Deleted.
+	(struct m68k_opcode_alias): New type.
+	(m68k_opcodes): Now const.  Deleted opcode aliases with exactly
+	matching constraints, values and flags.  As a side effect of this,
+	the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far
+	as I know were never used, now may need re-examining.
+	(numopcodes): Now const.
+	(m68k_opcode_aliases, numaliases): New variables.
+	(endop): Deleted.
+	[DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
+	m68k_opcode_aliases; update declaration of m68k_opcodes.
+
+
+Mon Mar  6 10:02:00 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (delay_type): Delete unused enumeration.
+	(pa_opcode): Replace unused delayed field with an architecture
+	field.
+	(pa_opcodes): Mark each instruction as either PA1.0 or PA1.1.
+
+Fri Mar  3 16:10:24 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (INSN_ISA4): Define.
+
+Fri Feb 24 19:13:37 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (M_DLA_AB, M_DLI): Define.
+
+Thu Feb 23 17:33:09 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (fstwx): Fix single-bit error.
+
+Wed Feb 15 12:19:52 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
+
+
+Mon Feb  6 10:35:23 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* i386.h: added cpuid instruction , and dr[0-7] aliases for the
+	  debug registers.  From Charles Hannum (mycroft@netbsd.org).
+
+Mon Feb  6 03:31:54 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit
+	i386 support:
+	* i386.h (MOV_AX_DISP32): New macro.
+	(i386_optab): Added Data16 and Data32 as needed.  Added "w" forms
+	of several call/return instructions.
+	(ADDR_PREFIX_OPCODE): New macro.
+
+Mon Jan 23 16:45:43 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	Sat Jan 21 17:50:38 1995  Pat Rankin  (rankin@eql.caltech.edu)
+
+	* ../include/opcode/vax.h (struct vot_wot, field `args'):  make
+	it pointer to const char;
+	(struct vot, field `name'):  ditto.
+
+Thu Jan 19 14:47:53 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* vax.h: Supply and properly group all values in end sentinel.
+
+Tue Jan 17 10:55:30 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* mips.h (INSN_ISA, INSN_4650): Define.
+
+
+
+Wed Oct 19 13:34:17 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* a29k.h: Add operand type 'I' for `inv' and `iretinv'.  On
+	systems with a separate instruction and data cache, such as the
+	29040, these instructions take an optional argument.
+
+Wed Sep 14 17:44:20 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* mips.h (INSN_STORE_MEMORY): Correct value to not conflict with
+	INSN_TRAP.
+
+Tue Sep  6 11:39:08 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* mips.h (INSN_STORE_MEMORY): Define.
+
+Thu Jul 28 19:28:07 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* sparc.h: Document new operand type 'x'.
+
+Tue Jul 26 17:48:05 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i960.h (I_CX2): New instruction category.  It includes
+	instructions available on Cx and Jx processors.
+	(I_JX): New instruction category, for JX-only instructions.
+	(i960_opcodes): Put eshro and sysctl in I_CX2 category.  Added
+	Jx-only instructions, in I_JX category.
+
+Wed Jul 13 18:43:47 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* ns32k.h (endop): Made pointer const too.
+
+Sun Jul 10 11:01:09 1994  Ian Dall  (dall@hfrd.dsto.gov.au)
+
+	* ns32k.h: Drop Q operand type as there is no correct use
+	for it. Add I and Z operand types which allow better checking.
+
+Thu Jul  7 12:34:48 1994  Steve Chamberlain  (sac@jonny.cygnus.com)
+
+	* h8300.h (xor.l) :fix bit pattern. 
+	(L_2): New size of operand.
+	(trapa): Use it.
+
+Fri Jun 10 16:38:11 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m68k.h: Move "trap" before "tpcc" to change disassembly.
+
+Fri Jun  3 15:57:36 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* sparc.h: Include v9 definitions.
+
+Thu Jun  2 12:23:17 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* m68k.h (m68060): Defined.
+	(m68040up, mfloat, mmmu): Include it.
+	(struct m68k_opcode): Widen `arch' field.
+	(m68k_opcodes): Updated for M68060.  Removed comments that were
+	instructions commented out by "JF" years ago.
+
+Thu Apr 28 18:31:14 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and
+	add a one-bit `flags' field.
+	(F_ALIAS): New macro.
+
+Wed Apr 27 11:29:52 1994  Steve Chamberlain  (sac@cygnus.com)
+
+	* h8300.h (dec, inc): Get encoding right.
+
+Mon Apr  4 13:12:43 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (struct powerpc_operand): Removed signedp field; just use
+	a flag instead.
+	(PPC_OPERAND_SIGNED): Define.
+	(PPC_OPERAND_SIGNOPT): Define.
+
+Thu Mar 31 19:34:08 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size
+	prefix is 0x66, not 0x67.  Patch from H.J. Lu (hlu@nynexst.com).
+
+Thu Mar  3 15:51:05 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h: Reverse last change.  It'll be handled in gas instead.
+
+Thu Feb 24 15:29:05 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h (sar): Disabled the two-operand Imm1 form, since it was
+	slower on the 486 and used the implicit shift count despite the
+	explicit operand.  The one-operand form is still available to get
+	the shorter form with the implicit shift count.
+
+Thu Feb 17 12:27:52 1994  Torbjorn Granlund  (tege@mexican.cygnus.com)
+
+	* hppa.h: Fix typo in fstws arg string.
+
+Wed Feb  9 21:23:52 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (struct powerpc_opcode): Make operands field unsigned.
+
+Mon Feb  7 19:14:58 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (PPC_OPCODE_601): Define.
+
+Fri Feb  4 23:43:50 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (addb): Use '@' for addb and addib pseudo ops.
+	(so we can determine valid completers for both addb and addb[tf].)
+
+	* hppa.h (xmpyu): No floating point format specifier for the
+	xmpyu instruction.
+
+Fri Feb  4 23:36:52 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (PPC_OPERAND_NEXT): Define.
+	(PPC_OPERAND_NEGATIVE): Change value to make room for above.
+	(struct powerpc_macro): Define.
+	(powerpc_macros, powerpc_num_macros): Declare.
+
+Fri Jan 21 19:13:50 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h: New file.  Header file for PowerPC opcode table.
+
+Mon Jan 17 00:14:23 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: More minor template fixes for sfu and copr (to allow
+	for easier disassembly).
+
+	* hppa.h: Fix templates for all the sfu and copr instructions.
+
+Wed Dec 15 15:12:42 1993  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h (push): Permit Imm16 operand too.
+
+Sat Dec 11 16:14:06 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	*  h8300.h (andc): Exists in base arch.
+
+Wed Dec  1 12:15:32 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>     
+	* hppa.h: #undef NONE to avoid conflict with hiux include files.
+
+Sun Nov 21 22:06:57 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: Add FP quadword store instructions.
+
+Wed Nov 17 17:13:16 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: (M_J_A): Added.
+	(M_LA): Removed.
+
+Mon Nov  8 12:12:47 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define.  From Ted Lemon
+	<mellon@pepper.ncd.com>.
+
+Sun Nov  7 00:30:11 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: Immediate field in probei instructions is unsigned,
+	not low-sign extended.
+
+Wed Nov  3 10:30:00 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00.
+
+Tue Nov  2 12:41:30 1993  Ken Raeburn  (raeburn@rover.cygnus.com)
+
+	* i386.h: Add "fxch" without operand.
+
+Mon Nov  1 18:13:03 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added.
+
+Sat Oct  2 22:26:11 1993  Jeffrey A Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: Add gfw and gfr to the opcode table.
+
+Wed Sep 29 16:23:00 1993  K. Richard Pixley  (rich@sendai.cygnus.com)
+
+	* m88k.h: extended to handle m88110.
+
+Tue Sep 28 19:19:08 1993  Jeffrey A Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (be, ble): Use operand type 'z' to denote absolute branch
+	addresses.
+
+Tue Sep 14 14:04:35 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* i960.h (i960_opcodes): Properly bracket initializers.
+
+Mon Sep 13 12:50:52 1993  K. Richard Pixley  (rich@sendai.cygnus.com)
+
+	* m88k.h (BOFLAG): rewrite to avoid nested comment.
+
+Mon Sep 13 15:46:06 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m68k.h (two): Protect second argument with parentheses.
+
+Fri Sep 10 16:29:47 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* i386.h (i386_optab): Added new instruction "rsm" (for i386sl).
+	Deleted old in/out instructions in "#if 0" section.
+
+Thu Sep  9 17:42:19 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* i386.h (i386_optab): Properly bracket initializers.
+
+Wed Aug 25 13:50:56 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* hppa.h (pa_opcode): Use '|' for movb and movib insns.  (From
+	Jeff Law, law@cs.utah.edu).
+
+Mon Aug 23 16:55:03 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* i386.h (lcall): Accept Imm32 operand also.
+
+Mon Aug 23 12:43:11 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (M_ABSU): Removed (absolute value of unsigned number??).
+	(M_DABS): Added.
+
+Thu Aug 19 15:08:37 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (INSN_*): Changed values.  Removed unused definitions.
+	Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3.  Split
+	INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and
+	INSN_LOAD_COPROC_DELAY.  Split INSN_COPROC_DELAY into
+	INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY.
+	(M_*): Added new values for r6000 and r4000 macros.
+	(ANY_DELAY): Removed.
+
+Wed Aug 18 15:37:48 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: Added M_LI_S and M_LI_SS.
+
+Tue Aug 17 07:08:08 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	* h8300.h: Get some rare mov.bs correct.
+
+Thu Aug  5 09:15:17 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* sparc.h: Don't define const ourself; rely on ansidecl.h having
+	been included.
+
+Fri Jul 30 18:41:11 1993  John Gilmore  (gnu@cygnus.com)
+
+	* sparc.h (F_JSR, F_UNBR, F_CONDBR):  Add new flags to mark
+	jump instructions, for use in disassemblers.
+
+Thu Jul 22 07:25:27 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* m88k.h: Make bitfields just unsigned, not unsigned long or
+	unsigned short.
+
+Wed Jul 21 11:55:31 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
+
+	* hppa.h: New argument type 'y'.  Use in various float instructions.
+
+Mon Jul 19 17:17:03 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
+
+	* hppa.h (break): First immediate field is unsigned.
+
+	* hppa.h: Add rfir instruction.
+
+Sun Jul 18 16:28:08 1993  Jim Kingdon  (kingdon@rtl.cygnus.com)
+
+	* mips.h: Split the actual table out into ../../opcodes/mips-opc.c.
+
+Fri Jul 16 09:59:29 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h: Reworked the hazard information somewhat, and fixed some
+	bugs in the instruction hazard descriptions.
+
+Thu Jul 15 12:42:01 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m88k.h: Corrected a couple of opcodes.
+
+Tue Jul  6 15:17:35 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h: Replaced with version from Ralph Campbell and OSF.  The
+	new version includes instruction hazard information, but is
+	otherwise reasonably similar.
+
+Thu Jul  1 20:36:17 1993  Doug Evans  (dje@canuck.cygnus.com)
+
+	* h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l).
+
+Fri Jun 11 18:38:44 1993  Ken Raeburn  (raeburn@cygnus.com)
+
+	Patches from Jeff Law, law@cs.utah.edu:
+	* hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
+	Make the tables be the same for the following instructions:
+	"bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", 
+	"sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
+	"ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", 
+	"comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", 
+	"frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", 
+	"fcmp", and "ftest".
+
+	* hppa.h: Make new and old tables the same for "break", "mtctl",
+	"mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub".
+	Fix typo in last patch.  Collapse several #ifdefs into a
+	single #ifdef.
+
+	* hppa.h: Delete remaining OLD_TABLE code.  Bring some
+	of the comments up-to-date.
+
+	* hppa.h: Update "free list" of letters and update
+	comments describing each letter's function.
+
+Fri Jun  4 15:41:37 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	* h8300.h: checkpoint, includes H8/300-H opcodes.
+
+Thu Jun  3 15:42:59 1993  Stu Grossman  (grossman@cygnus.com)
+
+	* Patches from Jeffrey Law <law@cs.utah.edu>.
+	* hppa.h: Rework single precision FP 
+	instructions so that they correctly disassemble code
+	PA1.1 code.
+
+Thu May 27 19:21:22 1993  Bruce Bauman  (boot@osf.org)
+
+	* i386.h (i386_optab, mov pattern): Remove Mem16 restriction from
+	mov to allow instructions like mov ss,xyz(ecx) to assemble.
+
+Tue May 25 00:39:40 1993  Ken Raeburn  (raeburn@cygnus.com)
+
+	* hppa.h: Use new version from Utah if OLD_TABLE isn't defined;
+	gdb will define it for now.
+
+Mon May 24 15:20:06 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* sparc.h: Don't end enumerator list with comma.
+
+Fri May 14 15:15:50 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson):
+	* mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define.
+	("bc2t"): Correct typo.
+	("[ls]wc[023]"): Use T rather than t.
+	("c[0123]"): Define general coprocessor instructions.
+
+Mon May 10 06:02:25 1993  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+
+	* m68k.h: Move split point for gcc compilation more towards
+	middle.
+
+Fri Apr  9 13:26:16 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* rs6k.h: Clean up instructions for primary opcode 19 (many were
+	simply wrong, ics, rfi, & rfsvc were missing).
+	Add "a" to opr_ext for "bb".  Doc fix.
+
+Thu Mar 18 13:45:31 1993  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* i386.h:  486 extensions from John Hassey (hassey@dg-rtp.dg.com).
+	* mips.h:  Add casts, to suppress warnings about shifting too much.
+	* m68k.h:  Document the placement code '9'.
+
+Thu Feb 18 02:03:14 1993  John Gilmore  (gnu@cygnus.com)
+
+	* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART):  Add kludge which
+	allows callers to break up the large initialized struct full of
+	opcodes into two half-sized ones.  This permits GCC to compile 
+	this module, since it takes exponential space for initializers.
+	(numopcodes, endop):  Revise to use AND_OTHER_PART in size calcs.
+
+Thu Feb  4 02:06:56 1993  John Gilmore  (gnu@cygnus.com)
+
+	* a29k.h:  Remove RCS crud, update GPL to v2, update copyrights.
+	* convex.h:  Added, from GDB's convx-opcode.h.  Added CONST to all
+	initialized structs in it.
+
+Thu Jan 28 21:32:22 1993  John Gilmore  (gnu@cygnus.com)
+
+	Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>:
+	* m88k.h (PMEM):  Avoid previous definition from <sys/param.h>.
+	(AND):  Change to AND_ to avoid ansidecl.h `AND' conflict.
+
+Sat Jan 23 18:10:49 PST 1993  Ralph Campbell  (ralphc@pyramid.com)
+
+	* mips.h: document "i" and "j" operands correctly.
+
+Thu Jan  7 15:58:13 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: Removed endianness dependency.
+
+Sun Jan  3 14:13:35 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* h8300.h: include info on number of cycles per instruction.
+
+Mon Dec 21 21:29:08 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* hppa.h:  Move handy aliases to the front.  Fix masks for extract
+	and deposit instructions.
+
+Sat Dec 12 16:09:48 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* i386.h: accept shld and shrd both with and without the shift
+	count argument, which is always %cl.
+
+Fri Nov 27 17:13:18 1992  Ken Raeburn  (raeburn at cygnus.com)
+
+	* i386.h (i386_optab_end, i386_regtab_end): Now const.
+	(one_byte_segment_defaults, two_byte_segment_defaults,
+	i386_prefixtab_end): Ditto.
+
+Mon Nov 23 10:47:25 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* vax.h (bb*): Use "v" (bitfield type), not "a" (address operand)
+	for operand 2; from John Carr, jfc@dsg.dec.com.
+
+Wed Nov  4 07:36:49 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions
+	always use 16-bit offsets.  Makes calculated-size jump tables
+	feasible.
+
+Fri Oct 16 22:52:43 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* i386.h: Fix one-operand forms of in* and out* patterns.
+
+Tue Sep 22 14:08:14 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* m68k.h: Added CPU32 support.
+
+Tue Sep 22 00:38:41 1992  John Gilmore  (gnu@cygnus.com)
+
+	* mips.h (break):  Disassemble the argument.  Patch from
+	jonathan@cs.stanford.edu (Jonathan Stone).
+
+Wed Sep  9 11:25:28 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* m68k.h: merged Motorola and MIT syntax.
+
+Thu Sep  3 09:33:22 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* m68k.h (pmove): make the tests less strict, the 68k book is
+	wrong.
+
+Tue Aug 25 23:25:19 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* m68k.h (m68ec030): Defined as alias for 68030.
+	(m68k_opcodes): New type characters "3" for 68030 MMU regs and "t"
+	for immediate 0-7 added.  Set up some opcodes (ptest, bkpt) to use
+	them.  Tightened description of "fmovex" to distinguish it from
+	some "pmove" encodings.  Added "pmove" for 68030 MMU regs, cleaned
+	up descriptions that claimed versions were available for chips not
+	supporting them.  Added "pmovefd".
+
+Mon Aug 24 12:04:51 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* m68k.h: fix where the . goes in divull
+
+Wed Aug 19 11:22:24 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* m68k.h: the cas2 instruction is supposed to be written with
+	indirection on the last two operands, which can be either data or
+	address registers.  Added a new operand type 'r' which accepts
+	either register type.  Added new cases for cas2l and cas2w which
+	use them.  Corrected masks for cas2 which failed to recognize use
+	of address register.
+
+Fri Aug 14 14:20:38 1992  Per Bothner  (bothner@cygnus.com)
+
+	* m68k.h:  Merged in patches (mostly m68040-specific) from
+	Colin Smith <colin@wrs.com>.
+
+	* m68k.h:  Merged m68kmri.h and m68k.h (using the former as a
+	base).  Also cleaned up duplicates, re-ordered instructions for
+	the sake of dis-assembling (so aliases come after standard names).
+	* m68kmri.h: Now just defines some macros, and #includes m68k.h.
+
+Wed Aug 12 16:38:15 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in
+	all missing .s
+
+Mon Aug 10 23:22:33 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* sparc.h: Moved tables to BFD library.
+
+	* i386.h (i386_optab): Add fildq, fistpq aliases used by gcc.
+
+Sun Jun 28 13:29:03 1992  Fred Fish  (fnf@cygnus.com)
+
+	* h8300.h:  Finish filling in all the holes in the opcode table,
+	so that the Lucid C compiler can digest this as well...
+
+Fri Jun 26 21:27:17 1992  John Gilmore  (gnu at cygnus.com)
+
+	* i386.h:  Add setc, setnc, addr16, data16, repz, repnz aliases.
+	Fix opcodes on various sizes of fild/fist instructions
+	(16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
+	Use tabs to indent for comments.  Fixes suggested by Minh Tran-Le.
+
+Thu Jun 25 16:13:26 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* h8300.h:  Fill in all the holes in the opcode table so that the
+	losing HPUX C compiler can digest this...
+
+Thu Jun 11 12:15:25 1992  John Gilmore  (gnu at cygnus.com)
+
+	* mips.h:  Fix decoding of coprocessor instructions, somewhat.
+	(Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.)
+
+Thu May 28 11:17:44 1992  Jim Wilson  (wilson@sphagnum.cygnus.com)
+
+	* sparc.h: Add new architecture variant sparclite; add its scan
+	and divscc opcodes.  Define ARCHITECTURES_CONFLICT_P macro.
+
+Tue May  5 14:23:27 1992  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* mips.h:  Add some more opcode synonyms (from Frank Yellin,
+	fy@lucid.com).
+
+Thu Apr 16 18:25:26 1992  Per Bothner  (bothner@cygnus.com)
+
+	* rs6k.h:  New version from IBM (Metin).
+
+Thu Apr  9 00:31:19 1992  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* rs6k.h: Fix incorrect extended opcode for instructions `fm'
+        and `fd'.  (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).)
+
+Tue Apr  7 13:38:47 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* rs6k.h:  Move from ../../gdb/rs6k-opcode.h.
+
+Fri Apr  3 11:30:20 1992  Fred Fish  (fnf@cygnus.com)
+
+	* m68k.h (one, two):  Cast macro args to unsigned to suppress
+	complaints from compiler and lint about integer overflow during
+	shift.
+
+Sun Mar 29 12:22:08 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sparc.h (OP):  Avoid signed overflow when shifting to high order bit.
+
+Fri Mar  6 00:22:38 1992  John Gilmore  (gnu at cygnus.com)
+
+	* mips.h:  Make bitfield layout depend on the HOST compiler,
+	not on the TARGET system.
+
+Fri Feb 21 01:29:51 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* i386.h: added inb, inw, outb, outw opcodes, added att syntax for
+	  scmp, slod, smov, ssca, ssto.  Curtesy Minh Tran-Le
+	  <TRANLE@INTELLICORP.COM>.
+
+Thu Jan 30 07:31:44 1992  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* h8300.h: turned op_type enum into #define list
+
+Thu Jan 30 01:07:24 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sparc.h:  Remove "cypress" architecture.  Remove "fitox" and
+	similar instructions -- they've been renamed to "fitoq", etc.
+	REALLY fix tsubcctv.  Fix "fcmpeq" and "fcmpq" which had wrong
+	number of arguments.
+	* h8300.h:  Remove extra ; which produces compiler warning.
+
+Tue Jan 28 22:59:22 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* sparc.h:  fix opcode for tsubcctv.
+
+Tue Jan  7 17:19:39 1992  K. Richard Pixley  (rich at cygnus.com)
+
+	* sparc.h: fba and cba are now aliases for fb and cb respectively.
+
+Fri Dec 27 10:55:50 1991  Per Bothner  (bothner at cygnus.com)
+
+	* sparc.h (nop):  Made the 'lose' field be even tighter,
+	so only a standard 'nop' is disassembled as a nop.
+
+Sun Dec 22 12:18:18 1991  Michael Tiemann  (tiemann at cygnus.com)
+
+	* sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
+	disassembled as a nop.
+
+Tue Dec 10 00:22:20 1991  K. Richard Pixley  (rich at rtl.cygnus.com)
+
+	* sparc.h: fix a typo.
+
+Sat Nov 30 20:40:51 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* a29k.h, arm.h, h8300.h,  i386.h,  i860.h, i960.h , m68k.h, 
+	m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
+	vax.h, ChangeLog: renamed from ../<foo>-opcode.h
+
+
+Local Variables:
+version-control: never
+End:
diff --git a/contrib/binutils/include/opcode/alpha.h b/contrib/binutils/include/opcode/alpha.h
new file mode 100644
index 000000000000..c3babc9f3701
--- /dev/null
+++ b/contrib/binutils/include/opcode/alpha.h
@@ -0,0 +1,237 @@
+/* alpha.h -- Header file for Alpha opcode table
+   Copyright 1996 Free Software Foundation, Inc.
+   Contributed by Richard Henderson <rth@tamu.edu>,
+   patterned after the PPC opcode table written by Ian Lance Taylor.
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef OPCODE_ALPHA_H
+#define OPCODE_ALPHA_H
+
+/* The opcode table is an array of struct alpha_opcode.  */
+
+struct alpha_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned mask;
+
+  /* One bit flags for the opcode.  These are primarily used to
+     indicate specific processors and environments support the
+     instructions.  The defined values are listed below. */
+  unsigned flags;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[4];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct alpha_opcode alpha_opcodes[];
+extern const int alpha_num_opcodes;
+
+/* Values defined for the flags field of a struct alpha_opcode.  */
+
+/* CPU Availability */
+#define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
+#define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
+#define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
+#define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
+#define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
+#define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
+
+#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5))
+
+/* A macro to extract the major opcode from an instruction.  */
+#define AXP_OP(i)	(((i) >> 26) & 0x3F)
+
+/* The total number of major opcodes. */
+#define AXP_NOPS	0x40
+
+
+/* The operands table is an array of struct alpha_operand.  */
+
+struct alpha_operand
+{
+  /* The number of bits in the operand.  */
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  int shift;
+
+  /* The default relocation type for this operand.  */
+  int default_reloc;
+
+  /* One bit syntax flags.  */
+  unsigned flags;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned (*insert) PARAMS ((unsigned instruction, int op,
+			      const char **errmsg));
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if ((o->flags & AXP_OPERAND_SIGNED) != 0
+	     && (op & (1 << (o->bits - 1))) != 0)
+	   op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  int (*extract) PARAMS ((unsigned instruction, int *invalid));
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the alpha_opcodes table.  */
+
+extern const struct alpha_operand alpha_operands[];
+extern const int alpha_num_operands;
+
+/* Values defined for the flags field of a struct alpha_operand.  */
+
+/* Mask for selecting the type for typecheck purposes */
+#define AXP_OPERAND_TYPECHECK_MASK					\
+  (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |		\
+   AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | 	\
+   AXP_OPERAND_UNSIGNED)
+
+/* This operand does not actually exist in the assembler input.  This
+   is used to support extended mnemonics, for which two operands fields
+   are identical.  The assembler should call the insert function with
+   any op value.  The disassembler should call the extract function,
+   ignore the return value, and check the value placed in the invalid
+   argument.  */
+#define AXP_OPERAND_FAKE	01
+
+/* The operand should be wrapped in parentheses rather than separated
+   from the previous by a comma.  This is used for the load and store
+   instructions which want their operands to look like "Ra,disp(Rb)".  */
+#define AXP_OPERAND_PARENS	02
+
+/* Used in combination with PARENS, this supresses the supression of
+   the comma.  This is used for "jmp Ra,(Rb),hint".  */
+#define AXP_OPERAND_COMMA	04
+
+/* This operand names an integer register.  */
+#define AXP_OPERAND_IR		010
+
+/* This operand names a floating point register.  */
+#define AXP_OPERAND_FPR		020
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define AXP_OPERAND_RELATIVE	040
+
+/* This operand takes signed values.  */
+#define AXP_OPERAND_SIGNED	0100
+
+/* This operand takes unsigned values.  This exists primarily so that
+   a flags value of 0 can be treated as end-of-arguments.  */
+#define AXP_OPERAND_UNSIGNED	0200
+
+/* Supress overflow detection on this field.  This is used for hints. */
+#define AXP_OPERAND_NOOVERFLOW	0400
+
+/* Mask for optional argument default value.  */
+#define AXP_OPERAND_OPTIONAL_MASK 07000
+
+/* This operand defaults to zero.  This is used for jump hints.  */
+#define AXP_OPERAND_DEFAULT_ZERO 01000
+
+/* This operand should default to the first (real) operand and is used
+   in conjunction with AXP_OPERAND_OPTIONAL.  This allows
+   "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
+   it, but it's what DEC does.  */
+#define AXP_OPERAND_DEFAULT_FIRST 02000
+
+/* Similarly, this operand should default to the second (real) operand.
+   This allows "negl $0" instead of "negl $0,$0".  */
+#define AXP_OPERAND_DEFAULT_SECOND 04000
+
+
+/* Register common names */
+
+#define AXP_REG_V0	0
+#define AXP_REG_T0	1
+#define AXP_REG_T1	2
+#define AXP_REG_T2	3
+#define AXP_REG_T3	4
+#define AXP_REG_T4	5
+#define AXP_REG_T5	6
+#define AXP_REG_T6	7
+#define AXP_REG_T7	8
+#define AXP_REG_S0	9
+#define AXP_REG_S1	10
+#define AXP_REG_S2	11
+#define AXP_REG_S3	12
+#define AXP_REG_S4	13
+#define AXP_REG_S5	14
+#define AXP_REG_FP	15
+#define AXP_REG_A0	16
+#define AXP_REG_A1	17
+#define AXP_REG_A2	18
+#define AXP_REG_A3	19
+#define AXP_REG_A4	20
+#define AXP_REG_A5	21
+#define AXP_REG_T8	22
+#define AXP_REG_T9	23
+#define AXP_REG_T10	24
+#define AXP_REG_T11	25
+#define AXP_REG_RA	26
+#define AXP_REG_PV	27
+#define AXP_REG_T12	27
+#define AXP_REG_AT	28
+#define AXP_REG_GP	29
+#define AXP_REG_SP	30
+#define AXP_REG_ZERO	31
+
+#endif /* OPCODE_ALPHA_H */
diff --git a/contrib/binutils/include/opcode/cgen.h b/contrib/binutils/include/opcode/cgen.h
new file mode 100644
index 000000000000..cda3373fd332
--- /dev/null
+++ b/contrib/binutils/include/opcode/cgen.h
@@ -0,0 +1,686 @@
+/* Header file for targets using CGEN: Cpu tools GENerator.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of GDB, the GNU debugger, and the GNU Binutils.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef CGEN_H
+#define CGEN_H
+
+#ifndef CGEN_CAT3
+#if defined(__STDC__) || defined(ALMOST_STDC)
+#define CGEN_XCAT3(a,b,c) a ## b ## c
+#define CGEN_CAT3(a,b,c) CGEN_XCAT3 (a, b, c)
+#else
+#define CGEN_CAT3(a,b,c) a/**/b/**/c
+#endif
+#endif
+
+/* Prepend the cpu name, defined in cpu-opc.h, and _cgen_ to symbol S.
+   The lack of spaces in the arg list is important for non-stdc systems.
+   This file is included by <cpu>-opc.h.
+   It can be included independently of cpu-opc.h, in which case the cpu
+   dependent portions will be declared as "unknown_cgen_foo".  */
+
+#ifndef CGEN_SYM
+#define CGEN_SYM(s) CGEN_CAT3 (unknown,_cgen_,s)
+#endif
+
+/* This file contains the static (unchanging) pieces and as much other stuff
+   as we can reasonably put here.  It's generally cleaner to put stuff here
+   rather than having it machine generated if possible.  */
+
+/* The assembler syntax is made up of expressions (duh...).
+   At the lowest level the values are mnemonics, register names, numbers, etc.
+   Above that are subexpressions, if any (an example might be the
+   "effective address" in m68k cpus).  At the second highest level are the
+   insns themselves.  Above that are pseudo-insns, synthetic insns, and macros,
+   if any.
+*/
+
+/* Lots of cpu's have a fixed insn size, or one which rarely changes,
+   and it's generally easier to handle these by treating the insn as an
+   integer type, rather than an array of characters.  So we allow targets
+   to control this.  */
+
+#ifdef CGEN_INT_INSN
+typedef unsigned int cgen_insn_t;
+#else
+typedef char *cgen_insn_t;
+#endif
+
+#ifdef __GNUC__
+#define CGEN_INLINE inline
+#else
+#define CGEN_INLINE
+#endif
+
+/* Perhaps we should just use bfd.h, but it's not clear
+   one would want to require that yet.  */
+enum cgen_endian {
+  CGEN_ENDIAN_UNKNOWN,
+  CGEN_ENDIAN_LITTLE,
+  CGEN_ENDIAN_BIG
+};
+
+/* Attributes.
+   Attributes are used to describe various random things.  */
+
+/* Struct to record attribute information.  */
+typedef struct {
+  unsigned int num_nonbools;
+  unsigned int bool;
+  unsigned int nonbool[1];
+} CGEN_ATTR;
+
+/* Define a structure member for attributes with N non-boolean entries.
+   The attributes are sorted so that the non-boolean ones come first.
+   num_nonbools: count of nonboolean attributes
+   bool: values of boolean attributes
+   nonbool: values of non-boolean attributes
+   There is a maximum of 32 attributes total.  */
+#define CGEN_ATTR_TYPE(n) \
+const struct { unsigned int num_nonbools; \
+	       unsigned int bool; \
+	       unsigned int nonbool[(n) ? (n) : 1]; }
+
+/* Given an attribute number, return its mask.  */
+#define CGEN_ATTR_MASK(attr) (1 << (attr))
+
+/* Return value of attribute ATTR in ATTR_TABLE for OBJ.
+   OBJ is a pointer to the entity that has the attributes.
+   It's not used at present but is reserved for future purposes.  */
+#define CGEN_ATTR_VALUE(obj, attr_table, attr) \
+((unsigned int) (attr) < (attr_table)->num_nonbools \
+ ? ((attr_table)->nonbool[attr]) \
+ : (((attr_table)->bool & (1 << (attr))) != 0))
+
+/* Parse result (also extraction result).
+
+   The result of parsing an insn is stored here.
+   To generate the actual insn, this is passed to the insert handler.
+   When printing an insn, the result of extraction is stored here.
+   To print the insn, this is passed to the print handler.
+
+   It is machine generated so we don't define it here,
+   but we do need a forward decl for the handler fns.
+
+   There is one member for each possible field in the insn.
+   The type depends on the field.
+   Also recorded here is the computed length of the insn for architectures
+   where it varies.
+*/
+
+struct cgen_fields;
+
+/* Total length of the insn, as recorded in the `fields' struct.  */
+/* ??? The field insert handler has lots of opportunities for optimization
+   if it ever gets inlined.  On architectures where insns all have the same
+   size, may wish to detect that and make this macro a constant - to allow
+   further optimizations.  */
+#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
+
+/* Associated with each insn or expression is a set of "handlers" for
+   performing operations like parsing, printing, etc.  */
+
+/* Forward decl.  */
+typedef struct cgen_insn CGEN_INSN;
+
+/* Parse handler.
+   The first argument is a pointer to a struct describing the insn being
+   parsed.
+   The second argument is a pointer to a pointer to the text being parsed.
+   The third argument is a pointer to a cgen_fields struct
+   in which the results are placed.
+   If the expression is successfully parsed, the pointer to the text is
+   updated.  If not it is left alone.
+   The result is NULL if success or an error message.  */
+typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *,
+					      const char **,
+					      struct cgen_fields *));
+
+/* Print handler.
+   The first argument is a pointer to the disassembly info.
+   Eg: disassemble_info.  It's defined as `PTR' so this file can be included
+   without dis-asm.h.
+   The second argument is a pointer to a struct describing the insn being
+   printed.
+   The third argument is a pointer to a cgen_fields struct.
+   The fourth argument is the pc value of the insn.
+   The fifth argument is the length of the insn, in bytes.  */
+/* Don't require bfd.h unnecessarily.  */
+#ifdef BFD_VERSION
+typedef void (cgen_print_fn) PARAMS ((PTR, const struct cgen_insn *,
+				      struct cgen_fields *, bfd_vma, int));
+#else
+typedef void (cgen_print_fn) ();
+#endif
+
+/* Insert handler.
+   The first argument is a pointer to a struct describing the insn being
+   parsed.
+   The second argument is a pointer to a cgen_fields struct
+   from which the values are fetched.
+   The third argument is a pointer to a buffer in which to place the insn.  */
+typedef void (cgen_insert_fn) PARAMS ((const struct cgen_insn *,
+				       struct cgen_fields *, cgen_insn_t *));
+
+/* Extract handler.
+   The first argument is a pointer to a struct describing the insn being
+   parsed.
+   The second argument is a pointer to a struct controlling extraction
+   (only used for variable length insns).
+   The third argument is the first CGEN_BASE_INSN_SIZE bytes.
+   The fourth argument is a pointer to a cgen_fields struct
+   in which the results are placed.
+   The result is the length of the insn or zero if not recognized.  */
+typedef int (cgen_extract_fn) PARAMS ((const struct cgen_insn *,
+				       void *, cgen_insn_t,
+				       struct cgen_fields *));
+
+/* The `parse' and `insert' fields are indices into these tables.
+   The elements are pointer to specialized handler functions.
+   Element 0 is special, it means use the default handler.  */
+extern cgen_parse_fn * CGEN_SYM (parse_handlers) [];
+#define CGEN_PARSE_FN(x) (CGEN_SYM (parse_handlers)[(x)->base.parse])
+extern cgen_insert_fn * CGEN_SYM (insert_handlers) [];
+#define CGEN_INSERT_FN(x) (CGEN_SYM (insert_handlers)[(x)->base.insert])
+
+/* Likewise for the `extract' and `print' fields.  */
+extern cgen_extract_fn * CGEN_SYM (extract_handlers) [];
+#define CGEN_EXTRACT_FN(x) (CGEN_SYM (extract_handlers)[(x)->base.extract])
+extern cgen_print_fn * CGEN_SYM (print_handlers) [];
+#define CGEN_PRINT_FN(x) (CGEN_SYM (print_handlers)[(x)->base.print])
+
+/* Base class of parser/printer.
+   (Don't read too much into the use of the phrase "base class").
+
+   Instructions and expressions all share this data in common.
+   It's a collection of the common elements needed to parse and print
+   each of them.  */
+
+#ifndef CGEN_MAX_INSN_ATTRS
+#define CGEN_MAX_INSN_ATTRS 1
+#endif
+
+struct cgen_base {
+  /* Indices into the handler tables.
+     We could use pointers here instead, but in the case of the insn table,
+     90% of them would be identical and that's a lot of redundant data.
+     0 means use the default (what the default is is up to the code).  */
+  unsigned char parse, insert, extract, print;
+
+  /* Attributes.  */
+  CGEN_ATTR_TYPE (CGEN_MAX_INSN_ATTRS) attrs;
+};
+
+/* Syntax table.
+
+   Each insn and subexpression has one of these.
+
+   The syntax "string" consists of characters (n > 0 && n < 128), and operand
+   values (n >= 128), and is terminated by 0.  Operand values are 128 + index
+   into the operand table.  The operand table doesn't exist in C, per se, as
+   the data is recorded in the parse/insert/extract/print switch statements.
+
+   ??? Whether we want to use yacc instead is unclear, but we do make an
+   effort to not make doing that difficult.  At least that's the intent.
+*/
+
+struct cgen_syntax {
+  /* Original syntax string, for debugging purposes.  */
+  char *orig;
+
+  /* Name of entry (that distinguishes it from all other entries).
+     This is used, for example, in simulator profiling results.  */
+  char *name;
+
+#if 0 /* not needed yet */
+  /* Format of this insn.
+     This doesn't closely follow the notion of instruction formats for more
+     complex instruction sets.  This is the value computed at runtime.  */
+  enum cgen_fmt_type fmt;
+#endif
+
+  /* Mnemonic (or name if expression).  */
+  char *mnemonic;
+
+  /* Syntax string.  */
+  /* FIXME: If each insn's mnemonic is constant, do we want to record just
+     the arguments here?  */
+#ifndef CGEN_MAX_SYNTAX_BYTES
+#define CGEN_MAX_SYNTAX_BYTES 16
+#endif
+  unsigned char syntax[CGEN_MAX_SYNTAX_BYTES];
+
+#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
+#define CGEN_SYNTAX_CHAR(c) (c)
+#define CGEN_SYNTAX_FIELD(c) ((c) - 128)
+
+  /* recognize insn if (op & mask) == value
+     For architectures with variable length insns, this is just a preliminary
+     test.  */
+  /* FIXME: Might want a selectable type (rather than always
+     unsigned long).  */
+  unsigned long mask, value;
+
+  /* length, in bits
+     This is the size that `mask' and `value' have been calculated to.
+     Normally it is CGEN_BASE_INSN_BITSIZE.  On vliw architectures where
+     the base insn size may be larger than the size of an insn, this field is
+     less than CGEN_BASE_INSN_BITSIZE.
+     On architectures like the 386 and m68k the real size of the insn may
+     be computed while parsing.  */
+  /* FIXME: wip, of course */
+  int length;
+};
+
+/* Operand values (keywords, integers, symbols, etc.)  */
+
+/* Types of assembler elements.  */
+
+enum cgen_asm_type {
+  CGEN_ASM_KEYWORD, CGEN_ASM_MAX
+};
+
+/* List of hardware elements.  */
+
+typedef struct cgen_hw_entry {
+  struct cgen_hw_entry *next;
+  char *name;
+  enum cgen_asm_type asm_type;
+  PTR asm_data;
+} CGEN_HW_ENTRY;
+
+extern CGEN_HW_ENTRY *CGEN_SYM (hw_list);
+
+CGEN_HW_ENTRY *cgen_hw_lookup PARAMS ((const char *));
+
+#ifndef CGEN_MAX_KEYWORD_ATTRS
+#define CGEN_MAX_KEYWORD_ATTRS 1
+#endif
+
+/* This struct is used to describe things like register names, etc.  */
+
+typedef struct cgen_keyword_entry {
+  /* Name (as in register name).  */
+  char *name;
+
+  /* Value (as in register number).
+     The value cannot be -1 as that is used to indicate "not found".
+     IDEA: Have "FUNCTION" attribute? [function is called to fetch value].  */
+  int value;
+
+  /* Attributes.  */
+  /* FIXME: Not used yet.  */
+  CGEN_ATTR_TYPE (CGEN_MAX_KEYWORD_ATTRS) attrs;
+
+  /* Next name hash table entry.  */
+  struct cgen_keyword_entry *next_name;
+  /* Next value hash table entry.  */
+  struct cgen_keyword_entry *next_value;
+} CGEN_KEYWORD_ENTRY;
+
+/* Top level struct for describing a set of related keywords
+   (e.g. register names).
+
+   This struct supports runtime entry of new values, and hashed lookups.  */
+
+typedef struct cgen_keyword {
+  /* Pointer to initial [compiled in] values.  */
+  struct cgen_keyword_entry *init_entries;
+  /* Number of entries in `init_entries'.  */
+  unsigned int num_init_entries;
+  /* Hash table used for name lookup.  */
+  struct cgen_keyword_entry **name_hash_table;
+  /* Hash table used for value lookup.  */
+  struct cgen_keyword_entry **value_hash_table;
+  /* Number of entries in the hash_tables.  */
+  unsigned int hash_table_size;
+} CGEN_KEYWORD;
+
+/* Structure used for searching.  */
+
+typedef struct cgen_keyword_search {
+  /* Table being searched.  */
+  const struct cgen_keyword *table;
+  /* Specification of what is being searched for.  */
+  const char *spec;
+  /* Current index in hash table.  */
+  unsigned int current_hash;
+  /* Current element in current hash chain.  */
+  struct cgen_keyword_entry *current_entry;
+} CGEN_KEYWORD_SEARCH;
+
+/* Lookup a keyword from its name.  */
+const struct cgen_keyword_entry * cgen_keyword_lookup_name
+  PARAMS ((struct cgen_keyword *, const char *));
+/* Lookup a keyword from its value.  */
+const struct cgen_keyword_entry * cgen_keyword_lookup_value
+  PARAMS ((struct cgen_keyword *, int));
+/* Add a keyword.  */
+void cgen_keyword_add PARAMS ((struct cgen_keyword *,
+			       struct cgen_keyword_entry *));
+/* Keyword searching.
+   This can be used to retrieve every keyword, or a subset.  */
+struct cgen_keyword_search cgen_keyword_search_init
+  PARAMS ((struct cgen_keyword *, const char *));
+const struct cgen_keyword_entry *cgen_keyword_search_next
+  PARAMS ((struct cgen_keyword_search *));
+
+/* Operand value support routines.  */
+/* FIXME: some of the long's here will need to be bfd_vma or some such.  */
+
+const char * cgen_parse_keyword PARAMS ((const char **,
+					 struct cgen_keyword *,
+					 long *));
+const char * cgen_parse_signed_integer PARAMS ((const char **, int,
+						long, long, long *));
+const char * cgen_parse_unsigned_integer PARAMS ((const char **, int,
+						  unsigned long, unsigned long,
+						  unsigned long *));
+const char * cgen_parse_address PARAMS ((const char **, int,
+					 int, long *));
+const char * cgen_validate_signed_integer PARAMS ((long, long, long));
+const char * cgen_validate_unsigned_integer PARAMS ((unsigned long,
+						     unsigned long,
+						     unsigned long));
+
+/* This struct defines each entry in the operand table.  */
+
+#ifndef CGEN_MAX_OPERAND_ATTRS
+#define CGEN_MAX_OPERAND_ATTRS 1
+#endif
+
+typedef struct cgen_operand {
+  /* For debugging.  */
+  char *name;
+
+  /* Bit position (msb of first byte = bit 0).
+     May be unused for a modifier.  */
+  unsigned char start;
+
+  /* The number of bits in the operand.
+     May be unused for a modifier.  */
+  unsigned char length;
+
+  /* Attributes.  */
+  CGEN_ATTR_TYPE (CGEN_MAX_OPERAND_ATTRS) attrs;
+#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
+
+#if 0 /* ??? Interesting idea but relocs tend to get too complicated for
+	 simple table lookups to work.  */
+  /* Ideally this would be the internal (external?) reloc type.  */
+  int reloc_type;
+#endif
+} CGEN_OPERAND;
+
+/* Return value of attribute ATTR in OPERAND.  */
+#define CGEN_OPERAND_ATTR(operand, attr) \
+CGEN_ATTR_VALUE (operand, CGEN_OPERAND_ATTRS (operand), attr)
+
+/* The operand table is currently a very static entity.  */
+extern const CGEN_OPERAND CGEN_SYM (operand_table)[];
+
+enum cgen_operand_type;
+
+#define CGEN_OPERAND_INDEX(operand) ((int) ((operand) - CGEN_SYM (operand_table)))
+/* FIXME: Rename, cpu-opc.h defines this as the typedef of the enum.  */
+#define CGEN_OPERAND_TYPE(operand) ((enum cgen_operand_type) CGEN_OPERAND_INDEX (operand))
+#define CGEN_OPERAND_ENTRY(n) (& CGEN_SYM (operand_table) [n])
+
+/* This struct defines each entry in the instruction table.  */
+
+struct cgen_insn {
+  struct cgen_base base;
+/* Given a pointer to a cgen_insn struct, return a pointer to `base'.  */
+#define CGEN_INSN_BASE(insn) (&(insn)->base)
+#define CGEN_INSN_ATTRS(insn) (&(insn)->base.attrs)
+
+  struct cgen_syntax syntax;
+#define CGEN_INSN_SYNTAX(insn) (&(insn)->syntax)
+#define CGEN_INSN_FMT(insn) ((insn)->syntax.fmt)
+#define CGEN_INSN_BITSIZE(insn) ((insn)->syntax.length)
+};
+
+/* Return value of attribute ATTR in INSN.  */
+#define CGEN_INSN_ATTR(insn, attr) \
+CGEN_ATTR_VALUE (insn, CGEN_INSN_ATTRS (insn), attr)
+
+/* Instruction lists.
+   This is used for adding new entries and for creating the hash lists.  */
+
+typedef struct cgen_insn_list {
+  struct cgen_insn_list *next;
+  const struct cgen_insn *insn;
+} CGEN_INSN_LIST;
+
+/* The table of instructions.  */
+
+typedef struct cgen_insn_table {
+  /* Pointer to initial [compiled in] entries.  */
+  const struct cgen_insn *init_entries;
+  /* Number of entries in `init_entries', including trailing NULL entry.  */
+  unsigned int num_init_entries;
+  /* Values added at runtime.  */
+  struct cgen_insn_list *new_entries;
+  /* Assembler hash function.  */
+  unsigned int (*asm_hash) PARAMS ((const char *));
+  /* Number of entries in assembler hash table.  */
+  unsigned int asm_hash_table_size;
+  /* Disassembler hash function.  */
+  unsigned int (*dis_hash) PARAMS ((const char *, unsigned long));
+  /* Number of entries in disassembler hash table.  */
+  unsigned int dis_hash_table_size;
+} CGEN_INSN_TABLE;
+
+/* ??? This is currently used by the simulator.
+   We want this to be fast and the simulator currently doesn't handle
+   runtime added instructions so this is ok.  An alternative would be to
+   store the index in the table.  */
+extern const CGEN_INSN CGEN_SYM (insn_table_entries)[];
+#define CGEN_INSN_INDEX(insn) ((int) ((insn) - CGEN_SYM (insn_table_entries)))
+#define CGEN_INSN_ENTRY(n) (& CGEN_SYM (insn_table_entries) [n])
+
+/* Return number of instructions.  This includes any added at runtime.  */
+
+int cgen_insn_count PARAMS (());
+
+/* The assembler insn table is hashed based on some function of the mnemonic
+   (the actually hashing done is up to the target, but we provide a few
+   examples like the first letter or a function of the entire mnemonic).
+   The index of each entry is the index of the corresponding table entry.
+   The value of each entry is the index of the next entry, with a 0
+   terminating (thus the first entry is reserved).  */
+
+#ifndef CGEN_ASM_HASH
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH_SIZE 127
+#define CGEN_ASM_HASH(string) (*(unsigned char *) (string) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH_SIZE 128
+#define CGEN_ASM_HASH(string) (*(unsigned char *) (string) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+unsigned int CGEN_SYM (asm_hash_insn) PARAMS ((const char *));
+CGEN_INSN_LIST * cgen_asm_lookup_insn PARAMS ((const char *));
+#define CGEN_ASM_LOOKUP_INSN(insn) cgen_asm_lookup_insn (insn)
+#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
+
+/* The disassembler insn table is hashed based on some function of machine
+   instruction (the actually hashing done is up to the target).  */
+
+/* It doesn't make much sense to provide a default here,
+   but while this is under development we do.
+   BUFFER is a pointer to the bytes of the insn.
+   INSN is the first CGEN_BASE_INSN_SIZE bytes as an int in host order.  */
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buffer, insn) (*(unsigned char *) (buffer))
+#endif
+
+unsigned int CGEN_SYM (dis_hash_insn) PARAMS ((const char *, unsigned long));
+CGEN_INSN_LIST * cgen_dis_lookup_insn PARAMS ((const char *, unsigned long));
+#define CGEN_DIS_LOOKUP_INSN(buf, insn) cgen_dis_lookup_insn (buf, insn)
+#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
+
+/* Top level structures and functions.  */
+
+typedef struct cgen_opcode_data {
+  CGEN_HW_ENTRY *hw_list;
+  /*CGEN_OPERAND_TABLE *operand_table; - FIXME:wip */
+  CGEN_INSN_TABLE *insn_table;
+} CGEN_OPCODE_DATA;
+
+/* Each CPU has one of these.  */
+extern CGEN_OPCODE_DATA CGEN_SYM (opcode_data);
+
+/* Global state access macros.
+   Some of these are tucked away and accessed with cover fns.
+   Simpler things like the current machine and endian are not.  */
+
+extern int cgen_current_machine;
+#define CGEN_CURRENT_MACHINE cgen_current_machine
+
+extern enum cgen_endian cgen_current_endian;
+#define CGEN_CURRENT_ENDIAN cgen_current_endian
+
+/* Prototypes of major functions.  */
+
+/* Set the current cpu (+ mach number, endian, etc.).  *?
+void cgen_set_cpu PARAMS ((CGEN_OPCODE_DATA *, int, enum cgen_endian));
+
+/* Initialize the assembler, disassembler.  */
+void cgen_asm_init PARAMS ((void));
+void cgen_dis_init PARAMS ((void));
+
+/* `init_tables' must be called before `xxx_supported'.  */
+void CGEN_SYM (init_tables) PARAMS ((int));
+void CGEN_SYM (init_asm) PARAMS ((int, enum cgen_endian));
+void CGEN_SYM (init_dis) PARAMS ((int, enum cgen_endian));
+void CGEN_SYM (init_parse) PARAMS ((void));
+void CGEN_SYM (init_print) PARAMS ((void));
+void CGEN_SYM (init_insert) PARAMS ((void));
+void CGEN_SYM (init_extract) PARAMS ((void));
+const struct cgen_insn *
+CGEN_SYM (assemble_insn) PARAMS ((const char *, struct cgen_fields *,
+				  cgen_insn_t *, char **));
+int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_syntax *));
+#if 0 /* old */
+int CGEN_SYM (opval_supported) PARAMS ((const struct cgen_opval *));
+#endif
+
+extern const struct cgen_keyword  CGEN_SYM (operand_mach);
+int CGEN_SYM (get_mach) PARAMS ((const char *));
+
+CGEN_INLINE void
+CGEN_SYM (put_operand) PARAMS ((int, const long *,
+				struct cgen_fields *));
+CGEN_INLINE long
+CGEN_SYM (get_operand) PARAMS ((int, const struct cgen_fields *));
+
+CGEN_INLINE const char *
+CGEN_SYM (parse_operand) PARAMS ((int, const char **, struct cgen_fields *));
+
+CGEN_INLINE const char *
+CGEN_SYM (validate_operand) PARAMS ((int, const struct cgen_fields *));
+
+/* Default insn parser, printer.  */
+extern cgen_parse_fn CGEN_SYM (parse_insn);
+extern cgen_insert_fn CGEN_SYM (insert_insn);
+extern cgen_extract_fn CGEN_SYM (extract_insn);
+extern cgen_print_fn CGEN_SYM (print_insn);
+
+/* Read in a cpu description file.  */
+const char * cgen_read_cpu_file PARAMS ((const char *));
+
+/* Assembler interface.
+
+   The interface to the assembler is intended to be clean in the sense that
+   libopcodes.a is a standalone entity and could be used with any assembler.
+   Not that one would necessarily want to do that but rather that it helps
+   keep a clean interface.  The interface will obviously be slanted towards
+   GAS, but at least it's a start.
+
+   Parsing is controlled by the assembler which calls
+   CGEN_SYM (assemble_insn).  If it can parse and build the entire insn
+   it doesn't call back to the assembler.  If it needs/wants to call back
+   to the assembler, (*cgen_parse_operand_fn) is called which can either
+
+   - return a number to be inserted in the insn
+   - return a "register" value to be inserted
+     (the register might not be a register per pe)
+   - queue the argument and return a marker saying the expression has been
+     queued (eg: a fix-up)
+   - return an error message indicating the expression wasn't recognizable
+
+   The result is an error message or NULL for success.
+   The parsed value is stored in the bfd_vma *.  */
+
+/* Values for indicating what the caller wants.  */
+enum cgen_parse_operand_type {
+  CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER,
+  CGEN_PARSE_OPERAND_ADDRESS
+};
+
+/* Values for indicating what was parsed.
+   ??? Not too useful at present but in time.  */
+enum cgen_parse_operand_result {
+  CGEN_PARSE_OPERAND_RESULT_NUMBER, CGEN_PARSE_OPERAND_RESULT_REGISTER,
+  CGEN_PARSE_OPERAND_RESULT_QUEUED, CGEN_PARSE_OPERAND_RESULT_ERROR
+};
+
+/* Don't require bfd.h unnecessarily.  */
+#ifdef BFD_VERSION
+extern const char * (*cgen_parse_operand_fn)
+     PARAMS ((enum cgen_parse_operand_type, const char **, int, int,
+	      enum cgen_parse_operand_result *, bfd_vma *));
+#endif
+
+/* Called before trying to match a table entry with the insn.  */
+void cgen_init_parse_operand PARAMS ((void));
+
+/* Called from <cpu>-asm.c to initialize operand parsing.  */
+
+/* These are GAS specific.  They're not here as part of the interface,
+   but rather that we need to put them somewhere.  */
+
+/* Call this from md_assemble to initialize the assembler callback.  */
+void cgen_asm_init_parse PARAMS ((void));
+
+/* Don't require bfd.h unnecessarily.  */
+#ifdef BFD_VERSION
+/* The result is an error message or NULL for success.
+   The parsed value is stored in the bfd_vma *.  */
+const char *cgen_parse_operand PARAMS ((enum cgen_parse_operand_type,
+					const char **, int, int,
+					enum cgen_parse_operand_result *,
+					bfd_vma *));
+#endif
+
+/* Add a register to the assembler's hash table.
+   This makes lets GAS parse registers for us.
+   ??? This isn't currently used, but it could be in the future.  */
+void cgen_asm_record_register PARAMS ((char *, int));
+
+/* After CGEN_SYM (assemble_insn) is done, this is called to
+   output the insn and record any fixups.  */
+void cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *,
+				   unsigned int));
+
+#endif /* CGEN_H */
diff --git a/contrib/binutils/include/opcode/convex.h b/contrib/binutils/include/opcode/convex.h
new file mode 100644
index 000000000000..efaeebb65a5f
--- /dev/null
+++ b/contrib/binutils/include/opcode/convex.h
@@ -0,0 +1,1711 @@
+/* Information for instruction disassembly on the Convex.
+   Copyright 1989, 1993 Free Software Foundation.  
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef	CONST
+#define	CONST
+#endif	/* CONST */
+
+#define xxx 0
+#define rrr 1
+#define rr 2
+#define rxr 3
+#define r 4
+#define nops 5
+#define nr 6
+#define pcrel 7
+#define lr 8
+#define rxl 9
+#define rlr 10
+#define rrl 11
+#define iml 12
+#define imr 13
+#define a1r 14
+#define a1l 15
+#define a2r 16
+#define a2l 17
+#define a3 18
+#define a4 19
+#define a5 20
+#define V 1
+#define S 2
+#define VM 3
+#define A 4
+#define VL 5
+#define VS 6
+#define VLS 7
+#define PSW 8
+/* Prevent an error during "make depend".  */
+#if !defined (PC)
+#define PC 9
+#endif
+#define ITR 10
+#define VV 11
+#define ITSR 12
+#define TOC 13
+#define CIR 14
+#define TTR 15
+#define VMU 16
+#define VML 17
+#define ICR 18
+#define TCPU 19
+#define CPUID 20
+#define TID 21
+
+CONST char *op[] = {
+  "",
+  "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7",
+  "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7",
+  "vm",
+  "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp",
+  "vl",
+  "vs",
+  "vls",
+  "psw",
+  "pc",
+  "itr",
+  "vv",
+  "itsr",
+  "toc",
+  "cir",
+  "ttr",
+  "vmu",
+  "vml",
+  "icr",
+  "tcpu",
+  "cpuid",
+  "tid",
+};
+
+CONST struct formstr format0[] = {
+  {0,0,rrr,V,S,S},	/* mov */
+  {0,0,rrr,S,S,V},	/* mov */
+  {1,1,rrr,V,V,V},	/* merg.t */
+  {2,1,rrr,V,V,V},	/* mask.t */
+  {1,2,rrr,V,S,V},	/* merg.f */
+  {2,2,rrr,V,S,V},	/* mask.f */
+  {1,1,rrr,V,S,V},	/* merg.t */
+  {2,1,rrr,V,S,V},	/* mask.t */
+  {3,3,rrr,V,V,V},	/* mul.s */
+  {3,4,rrr,V,V,V},	/* mul.d */
+  {4,3,rrr,V,V,V},	/* div.s */
+  {4,4,rrr,V,V,V},	/* div.d */
+  {3,3,rrr,V,S,V},	/* mul.s */
+  {3,4,rrr,V,S,V},	/* mul.d */
+  {4,3,rrr,V,S,V},	/* div.s */
+  {4,4,rrr,V,S,V},	/* div.d */
+  {5,0,rrr,V,V,V},	/* and */
+  {6,0,rrr,V,V,V},	/* or */
+  {7,0,rrr,V,V,V},	/* xor */
+  {8,0,rrr,V,V,V},	/* shf */
+  {5,0,rrr,V,S,V},	/* and */
+  {6,0,rrr,V,S,V},	/* or */
+  {7,0,rrr,V,S,V},	/* xor */
+  {8,0,rrr,V,S,V},	/* shf */
+  {9,3,rrr,V,V,V},	/* add.s */
+  {9,4,rrr,V,V,V},	/* add.d */
+  {10,3,rrr,V,V,V},	/* sub.s */
+  {10,4,rrr,V,V,V},	/* sub.d */
+  {9,3,rrr,V,S,V},	/* add.s */
+  {9,4,rrr,V,S,V},	/* add.d */
+  {10,3,rrr,V,S,V},	/* sub.s */
+  {10,4,rrr,V,S,V},	/* sub.d */
+  {9,5,rrr,V,V,V},	/* add.b */
+  {9,6,rrr,V,V,V},	/* add.h */
+  {9,7,rrr,V,V,V},	/* add.w */
+  {9,8,rrr,V,V,V},	/* add.l */
+  {9,5,rrr,V,S,V},	/* add.b */
+  {9,6,rrr,V,S,V},	/* add.h */
+  {9,7,rrr,V,S,V},	/* add.w */
+  {9,8,rrr,V,S,V},	/* add.l */
+  {10,5,rrr,V,V,V},	/* sub.b */
+  {10,6,rrr,V,V,V},	/* sub.h */
+  {10,7,rrr,V,V,V},	/* sub.w */
+  {10,8,rrr,V,V,V},	/* sub.l */
+  {10,5,rrr,V,S,V},	/* sub.b */
+  {10,6,rrr,V,S,V},	/* sub.h */
+  {10,7,rrr,V,S,V},	/* sub.w */
+  {10,8,rrr,V,S,V},	/* sub.l */
+  {3,5,rrr,V,V,V},	/* mul.b */
+  {3,6,rrr,V,V,V},	/* mul.h */
+  {3,7,rrr,V,V,V},	/* mul.w */
+  {3,8,rrr,V,V,V},	/* mul.l */
+  {3,5,rrr,V,S,V},	/* mul.b */
+  {3,6,rrr,V,S,V},	/* mul.h */
+  {3,7,rrr,V,S,V},	/* mul.w */
+  {3,8,rrr,V,S,V},	/* mul.l */
+  {4,5,rrr,V,V,V},	/* div.b */
+  {4,6,rrr,V,V,V},	/* div.h */
+  {4,7,rrr,V,V,V},	/* div.w */
+  {4,8,rrr,V,V,V},	/* div.l */
+  {4,5,rrr,V,S,V},	/* div.b */
+  {4,6,rrr,V,S,V},	/* div.h */
+  {4,7,rrr,V,S,V},	/* div.w */
+  {4,8,rrr,V,S,V},	/* div.l */
+};
+
+CONST struct formstr format1[] = {
+  {11,0,xxx,0,0,0},	/* exit */
+  {12,0,a3,0,0,0},	/* jmp */
+  {13,2,a3,0,0,0},	/* jmpi.f */
+  {13,1,a3,0,0,0},	/* jmpi.t */
+  {14,2,a3,0,0,0},	/* jmpa.f */
+  {14,1,a3,0,0,0},	/* jmpa.t */
+  {15,2,a3,0,0,0},	/* jmps.f */
+  {15,1,a3,0,0,0},	/* jmps.t */
+  {16,0,a3,0,0,0},	/* tac */
+  {17,0,a1r,A,0,0},	/* ldea */
+  {18,8,a1l,VLS,0,0},	/* ld.l */
+  {18,9,a1l,VM,0,0},	/* ld.x */
+  {19,0,a3,0,0,0},	/* tas */
+  {20,0,a3,0,0,0},	/* pshea */
+  {21,8,a2l,VLS,0,0},	/* st.l */
+  {21,9,a2l,VM,0,0},	/* st.x */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {22,0,a3,0,0,0},	/* call */
+  {23,0,a3,0,0,0},	/* calls */
+  {24,0,a3,0,0,0},	/* callq */
+  {25,0,a1r,A,0,0},	/* pfork */
+  {26,5,a2r,S,0,0},	/* ste.b */
+  {26,6,a2r,S,0,0},	/* ste.h */
+  {26,7,a2r,S,0,0},	/* ste.w */
+  {26,8,a2r,S,0,0},	/* ste.l */
+  {18,5,a1r,A,0,0},	/* ld.b */
+  {18,6,a1r,A,0,0},	/* ld.h */
+  {18,7,a1r,A,0,0},	/* ld.w */
+  {27,7,a1r,A,0,0},	/* incr.w */
+  {21,5,a2r,A,0,0},	/* st.b */
+  {21,6,a2r,A,0,0},	/* st.h */
+  {21,7,a2r,A,0,0},	/* st.w */
+  {27,8,a1r,S,0,0},	/* incr.l */
+  {18,5,a1r,S,0,0},	/* ld.b */
+  {18,6,a1r,S,0,0},	/* ld.h */
+  {18,7,a1r,S,0,0},	/* ld.w */
+  {18,8,a1r,S,0,0},	/* ld.l */
+  {21,5,a2r,S,0,0},	/* st.b */
+  {21,6,a2r,S,0,0},	/* st.h */
+  {21,7,a2r,S,0,0},	/* st.w */
+  {21,8,a2r,S,0,0},	/* st.l */
+  {18,5,a1r,V,0,0},	/* ld.b */
+  {18,6,a1r,V,0,0},	/* ld.h */
+  {18,7,a1r,V,0,0},	/* ld.w */
+  {18,8,a1r,V,0,0},	/* ld.l */
+  {21,5,a2r,V,0,0},	/* st.b */
+  {21,6,a2r,V,0,0},	/* st.h */
+  {21,7,a2r,V,0,0},	/* st.w */
+  {21,8,a2r,V,0,0},	/* st.l */
+};
+
+CONST struct formstr format2[] = {
+  {28,5,rr,A,A,0},	/* cvtw.b */
+  {28,6,rr,A,A,0},	/* cvtw.h */
+  {29,7,rr,A,A,0},	/* cvtb.w */
+  {30,7,rr,A,A,0},	/* cvth.w */
+  {28,5,rr,S,S,0},	/* cvtw.b */
+  {28,6,rr,S,S,0},	/* cvtw.h */
+  {29,7,rr,S,S,0},	/* cvtb.w */
+  {30,7,rr,S,S,0},	/* cvth.w */
+  {28,3,rr,S,S,0},	/* cvtw.s */
+  {31,7,rr,S,S,0},	/* cvts.w */
+  {32,3,rr,S,S,0},	/* cvtd.s */
+  {31,4,rr,S,S,0},	/* cvts.d */
+  {31,8,rr,S,S,0},	/* cvts.l */
+  {32,8,rr,S,S,0},	/* cvtd.l */
+  {33,3,rr,S,S,0},	/* cvtl.s */
+  {33,4,rr,S,S,0},	/* cvtl.d */
+  {34,0,rr,A,A,0},	/* ldpa */
+  {8,0,nr,A,0,0},	/* shf */
+  {18,6,nr,A,0,0},	/* ld.h */
+  {18,7,nr,A,0,0},	/* ld.w */
+  {33,7,rr,S,S,0},	/* cvtl.w */
+  {28,8,rr,S,S,0},	/* cvtw.l */
+  {35,1,rr,S,S,0},	/* plc.t */
+  {36,0,rr,S,S,0},	/* tzc */
+  {37,6,rr,A,A,0},	/* eq.h */
+  {37,7,rr,A,A,0},	/* eq.w */
+  {37,6,nr,A,0,0},	/* eq.h */
+  {37,7,nr,A,0,0},	/* eq.w */
+  {37,5,rr,S,S,0},	/* eq.b */
+  {37,6,rr,S,S,0},	/* eq.h */
+  {37,7,rr,S,S,0},	/* eq.w */
+  {37,8,rr,S,S,0},	/* eq.l */
+  {38,6,rr,A,A,0},	/* leu.h */
+  {38,7,rr,A,A,0},	/* leu.w */
+  {38,6,nr,A,0,0},	/* leu.h */
+  {38,7,nr,A,0,0},	/* leu.w */
+  {38,5,rr,S,S,0},	/* leu.b */
+  {38,6,rr,S,S,0},	/* leu.h */
+  {38,7,rr,S,S,0},	/* leu.w */
+  {38,8,rr,S,S,0},	/* leu.l */
+  {39,6,rr,A,A,0},	/* ltu.h */
+  {39,7,rr,A,A,0},	/* ltu.w */
+  {39,6,nr,A,0,0},	/* ltu.h */
+  {39,7,nr,A,0,0},	/* ltu.w */
+  {39,5,rr,S,S,0},	/* ltu.b */
+  {39,6,rr,S,S,0},	/* ltu.h */
+  {39,7,rr,S,S,0},	/* ltu.w */
+  {39,8,rr,S,S,0},	/* ltu.l */
+  {40,6,rr,A,A,0},	/* le.h */
+  {40,7,rr,A,A,0},	/* le.w */
+  {40,6,nr,A,0,0},	/* le.h */
+  {40,7,nr,A,0,0},	/* le.w */
+  {40,5,rr,S,S,0},	/* le.b */
+  {40,6,rr,S,S,0},	/* le.h */
+  {40,7,rr,S,S,0},	/* le.w */
+  {40,8,rr,S,S,0},	/* le.l */
+  {41,6,rr,A,A,0},	/* lt.h */
+  {41,7,rr,A,A,0},	/* lt.w */
+  {41,6,nr,A,0,0},	/* lt.h */
+  {41,7,nr,A,0,0},	/* lt.w */
+  {41,5,rr,S,S,0},	/* lt.b */
+  {41,6,rr,S,S,0},	/* lt.h */
+  {41,7,rr,S,S,0},	/* lt.w */
+  {41,8,rr,S,S,0},	/* lt.l */
+  {9,7,rr,S,A,0},	/* add.w */
+  {8,0,rr,A,A,0},	/* shf */
+  {0,0,rr,A,A,0},	/* mov */
+  {0,0,rr,S,A,0},	/* mov */
+  {0,7,rr,S,S,0},	/* mov.w */
+  {8,0,rr,S,S,0},	/* shf */
+  {0,0,rr,S,S,0},	/* mov */
+  {0,0,rr,A,S,0},	/* mov */
+  {5,0,rr,A,A,0},	/* and */
+  {6,0,rr,A,A,0},	/* or */
+  {7,0,rr,A,A,0},	/* xor */
+  {42,0,rr,A,A,0},	/* not */
+  {5,0,rr,S,S,0},	/* and */
+  {6,0,rr,S,S,0},	/* or */
+  {7,0,rr,S,S,0},	/* xor */
+  {42,0,rr,S,S,0},	/* not */
+  {40,3,rr,S,S,0},	/* le.s */
+  {40,4,rr,S,S,0},	/* le.d */
+  {41,3,rr,S,S,0},	/* lt.s */
+  {41,4,rr,S,S,0},	/* lt.d */
+  {9,3,rr,S,S,0},	/* add.s */
+  {9,4,rr,S,S,0},	/* add.d */
+  {10,3,rr,S,S,0},	/* sub.s */
+  {10,4,rr,S,S,0},	/* sub.d */
+  {37,3,rr,S,S,0},	/* eq.s */
+  {37,4,rr,S,S,0},	/* eq.d */
+  {43,6,rr,A,A,0},	/* neg.h */
+  {43,7,rr,A,A,0},	/* neg.w */
+  {3,3,rr,S,S,0},	/* mul.s */
+  {3,4,rr,S,S,0},	/* mul.d */
+  {4,3,rr,S,S,0},	/* div.s */
+  {4,4,rr,S,S,0},	/* div.d */
+  {9,6,rr,A,A,0},	/* add.h */
+  {9,7,rr,A,A,0},	/* add.w */
+  {9,6,nr,A,0,0},	/* add.h */
+  {9,7,nr,A,0,0},	/* add.w */
+  {9,5,rr,S,S,0},	/* add.b */
+  {9,6,rr,S,S,0},	/* add.h */
+  {9,7,rr,S,S,0},	/* add.w */
+  {9,8,rr,S,S,0},	/* add.l */
+  {10,6,rr,A,A,0},	/* sub.h */
+  {10,7,rr,A,A,0},	/* sub.w */
+  {10,6,nr,A,0,0},	/* sub.h */
+  {10,7,nr,A,0,0},	/* sub.w */
+  {10,5,rr,S,S,0},	/* sub.b */
+  {10,6,rr,S,S,0},	/* sub.h */
+  {10,7,rr,S,S,0},	/* sub.w */
+  {10,8,rr,S,S,0},	/* sub.l */
+  {3,6,rr,A,A,0},	/* mul.h */
+  {3,7,rr,A,A,0},	/* mul.w */
+  {3,6,nr,A,0,0},	/* mul.h */
+  {3,7,nr,A,0,0},	/* mul.w */
+  {3,5,rr,S,S,0},	/* mul.b */
+  {3,6,rr,S,S,0},	/* mul.h */
+  {3,7,rr,S,S,0},	/* mul.w */
+  {3,8,rr,S,S,0},	/* mul.l */
+  {4,6,rr,A,A,0},	/* div.h */
+  {4,7,rr,A,A,0},	/* div.w */
+  {4,6,nr,A,0,0},	/* div.h */
+  {4,7,nr,A,0,0},	/* div.w */
+  {4,5,rr,S,S,0},	/* div.b */
+  {4,6,rr,S,S,0},	/* div.h */
+  {4,7,rr,S,S,0},	/* div.w */
+  {4,8,rr,S,S,0},	/* div.l */
+};
+
+CONST struct formstr format3[] = {
+  {32,3,rr,V,V,0},	/* cvtd.s */
+  {31,4,rr,V,V,0},	/* cvts.d */
+  {33,4,rr,V,V,0},	/* cvtl.d */
+  {32,8,rr,V,V,0},	/* cvtd.l */
+  {0,0,rrl,S,S,VM},	/* mov */
+  {0,0,rlr,S,VM,S},	/* mov */
+  {0,0,0,0,0,0},
+  {44,0,rr,S,S,0},	/* lop */
+  {36,0,rr,V,V,0},	/* tzc */
+  {44,0,rr,V,V,0},	/* lop */
+  {0,0,0,0,0,0},
+  {42,0,rr,V,V,0},	/* not */
+  {8,0,rr,S,V,0},	/* shf */
+  {35,1,rr,V,V,0},	/* plc.t */
+  {45,2,rr,V,V,0},	/* cprs.f */
+  {45,1,rr,V,V,0},	/* cprs.t */
+  {37,3,rr,V,V,0},	/* eq.s */
+  {37,4,rr,V,V,0},	/* eq.d */
+  {43,3,rr,V,V,0},	/* neg.s */
+  {43,4,rr,V,V,0},	/* neg.d */
+  {37,3,rr,S,V,0},	/* eq.s */
+  {37,4,rr,S,V,0},	/* eq.d */
+  {43,3,rr,S,S,0},	/* neg.s */
+  {43,4,rr,S,S,0},	/* neg.d */
+  {40,3,rr,V,V,0},	/* le.s */
+  {40,4,rr,V,V,0},	/* le.d */
+  {41,3,rr,V,V,0},	/* lt.s */
+  {41,4,rr,V,V,0},	/* lt.d */
+  {40,3,rr,S,V,0},	/* le.s */
+  {40,4,rr,S,V,0},	/* le.d */
+  {41,3,rr,S,V,0},	/* lt.s */
+  {41,4,rr,S,V,0},	/* lt.d */
+  {37,5,rr,V,V,0},	/* eq.b */
+  {37,6,rr,V,V,0},	/* eq.h */
+  {37,7,rr,V,V,0},	/* eq.w */
+  {37,8,rr,V,V,0},	/* eq.l */
+  {37,5,rr,S,V,0},	/* eq.b */
+  {37,6,rr,S,V,0},	/* eq.h */
+  {37,7,rr,S,V,0},	/* eq.w */
+  {37,8,rr,S,V,0},	/* eq.l */
+  {40,5,rr,V,V,0},	/* le.b */
+  {40,6,rr,V,V,0},	/* le.h */
+  {40,7,rr,V,V,0},	/* le.w */
+  {40,8,rr,V,V,0},	/* le.l */
+  {40,5,rr,S,V,0},	/* le.b */
+  {40,6,rr,S,V,0},	/* le.h */
+  {40,7,rr,S,V,0},	/* le.w */
+  {40,8,rr,S,V,0},	/* le.l */
+  {41,5,rr,V,V,0},	/* lt.b */
+  {41,6,rr,V,V,0},	/* lt.h */
+  {41,7,rr,V,V,0},	/* lt.w */
+  {41,8,rr,V,V,0},	/* lt.l */
+  {41,5,rr,S,V,0},	/* lt.b */
+  {41,6,rr,S,V,0},	/* lt.h */
+  {41,7,rr,S,V,0},	/* lt.w */
+  {41,8,rr,S,V,0},	/* lt.l */
+  {43,5,rr,V,V,0},	/* neg.b */
+  {43,6,rr,V,V,0},	/* neg.h */
+  {43,7,rr,V,V,0},	/* neg.w */
+  {43,8,rr,V,V,0},	/* neg.l */
+  {43,5,rr,S,S,0},	/* neg.b */
+  {43,6,rr,S,S,0},	/* neg.h */
+  {43,7,rr,S,S,0},	/* neg.w */
+  {43,8,rr,S,S,0},	/* neg.l */
+};
+
+CONST struct formstr format4[] = {
+  {46,0,nops,0,0,0},	/* nop */
+  {47,0,pcrel,0,0,0},	/* br */
+  {48,2,pcrel,0,0,0},	/* bri.f */
+  {48,1,pcrel,0,0,0},	/* bri.t */
+  {49,2,pcrel,0,0,0},	/* bra.f */
+  {49,1,pcrel,0,0,0},	/* bra.t */
+  {50,2,pcrel,0,0,0},	/* brs.f */
+  {50,1,pcrel,0,0,0},	/* brs.t */
+};
+
+CONST struct formstr format5[] = {
+  {51,5,rr,V,V,0},	/* ldvi.b */
+  {51,6,rr,V,V,0},	/* ldvi.h */
+  {51,7,rr,V,V,0},	/* ldvi.w */
+  {51,8,rr,V,V,0},	/* ldvi.l */
+  {28,3,rr,V,V,0},	/* cvtw.s */
+  {31,7,rr,V,V,0},	/* cvts.w */
+  {28,8,rr,V,V,0},	/* cvtw.l */
+  {33,7,rr,V,V,0},	/* cvtl.w */
+  {52,5,rxr,V,V,0},	/* stvi.b */
+  {52,6,rxr,V,V,0},	/* stvi.h */
+  {52,7,rxr,V,V,0},	/* stvi.w */
+  {52,8,rxr,V,V,0},	/* stvi.l */
+  {52,5,rxr,S,V,0},	/* stvi.b */
+  {52,6,rxr,S,V,0},	/* stvi.h */
+  {52,7,rxr,S,V,0},	/* stvi.w */
+  {52,8,rxr,S,V,0},	/* stvi.l */
+};
+
+CONST struct formstr format6[] = {
+  {53,0,r,A,0,0},	/* ldsdr */
+  {54,0,r,A,0,0},	/* ldkdr */
+  {55,3,r,S,0,0},	/* ln.s */
+  {55,4,r,S,0,0},	/* ln.d */
+  {56,0,nops,0,0,0},	/* patu */
+  {57,0,r,A,0,0},	/* pate */
+  {58,0,nops,0,0,0},	/* pich */
+  {59,0,nops,0,0,0},	/* plch */
+  {0,0,lr,PSW,A,0},	/* mov */
+  {0,0,rxl,A,PSW,0},	/* mov */
+  {0,0,lr,PC,A,0},	/* mov */
+  {60,0,r,S,0,0},	/* idle */
+  {0,0,lr,ITR,S,0},	/* mov */
+  {0,0,rxl,S,ITR,0},	/* mov */
+  {0,0,0,0,0,0},
+  {0,0,rxl,S,ITSR,0},	/* mov */
+  {61,0,nops,0,0,0},	/* rtnq */
+  {62,0,nops,0,0,0},	/* cfork */
+  {63,0,nops,0,0,0},	/* rtn */
+  {64,0,nops,0,0,0},	/* wfork */
+  {65,0,nops,0,0,0},	/* join */
+  {66,0,nops,0,0,0},	/* rtnc */
+  {67,3,r,S,0,0},	/* exp.s */
+  {67,4,r,S,0,0},	/* exp.d */
+  {68,3,r,S,0,0},	/* sin.s */
+  {68,4,r,S,0,0},	/* sin.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {69,3,r,S,0,0},	/* cos.s */
+  {69,4,r,S,0,0},	/* cos.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {70,7,r,A,0,0},	/* psh.w */
+  {0,0,0,0,0,0},
+  {71,7,r,A,0,0},	/* pop.w */
+  {0,0,0,0,0,0},
+  {70,7,r,S,0,0},	/* psh.w */
+  {70,8,r,S,0,0},	/* psh.l */
+  {71,7,r,S,0,0},	/* pop.w */
+  {71,8,r,S,0,0},	/* pop.l */
+  {72,0,nops,0,0,0},	/* eni */
+  {73,0,nops,0,0,0},	/* dsi */
+  {74,0,nops,0,0,0},	/* bkpt */
+  {75,0,nops,0,0,0},	/* msync */
+  {76,0,r,S,0,0},	/* mski */
+  {77,0,r,S,0,0},	/* xmti */
+  {0,0,rxl,S,VV,0},	/* mov */
+  {78,0,nops,0,0,0},	/* tstvv */
+  {0,0,lr,VS,A,0},	/* mov */
+  {0,0,rxl,A,VS,0},	/* mov */
+  {0,0,lr,VL,A,0},	/* mov */
+  {0,0,rxl,A,VL,0},	/* mov */
+  {0,7,lr,VS,S,0},	/* mov.w */
+  {0,7,rxl,S,VS,0},	/* mov.w */
+  {0,7,lr,VL,S,0},	/* mov.w */
+  {0,7,rxl,S,VL,0},	/* mov.w */
+  {79,0,r,A,0,0},	/* diag */
+  {80,0,nops,0,0,0},	/* pbkpt */
+  {81,3,r,S,0,0},	/* sqrt.s */
+  {81,4,r,S,0,0},	/* sqrt.d */
+  {82,0,nops,0,0,0},	/* casr */
+  {0,0,0,0,0,0},
+  {83,3,r,S,0,0},	/* atan.s */
+  {83,4,r,S,0,0},	/* atan.d */
+};
+
+CONST struct formstr format7[] = {
+  {84,5,r,V,0,0},	/* sum.b */
+  {84,6,r,V,0,0},	/* sum.h */
+  {84,7,r,V,0,0},	/* sum.w */
+  {84,8,r,V,0,0},	/* sum.l */
+  {85,0,r,V,0,0},	/* all */
+  {86,0,r,V,0,0},	/* any */
+  {87,0,r,V,0,0},	/* parity */
+  {0,0,0,0,0,0},
+  {88,5,r,V,0,0},	/* max.b */
+  {88,6,r,V,0,0},	/* max.h */
+  {88,7,r,V,0,0},	/* max.w */
+  {88,8,r,V,0,0},	/* max.l */
+  {89,5,r,V,0,0},	/* min.b */
+  {89,6,r,V,0,0},	/* min.h */
+  {89,7,r,V,0,0},	/* min.w */
+  {89,8,r,V,0,0},	/* min.l */
+  {84,3,r,V,0,0},	/* sum.s */
+  {84,4,r,V,0,0},	/* sum.d */
+  {90,3,r,V,0,0},	/* prod.s */
+  {90,4,r,V,0,0},	/* prod.d */
+  {88,3,r,V,0,0},	/* max.s */
+  {88,4,r,V,0,0},	/* max.d */
+  {89,3,r,V,0,0},	/* min.s */
+  {89,4,r,V,0,0},	/* min.d */
+  {90,5,r,V,0,0},	/* prod.b */
+  {90,6,r,V,0,0},	/* prod.h */
+  {90,7,r,V,0,0},	/* prod.w */
+  {90,8,r,V,0,0},	/* prod.l */
+  {35,2,lr,VM,S,0},	/* plc.f */
+  {35,1,lr,VM,S,0},	/* plc.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr formatx[] = {
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr format1a[] = {
+  {91,0,imr,A,0,0},	/* halt */
+  {92,0,a4,0,0,0},	/* sysc */
+  {18,6,imr,A,0,0},	/* ld.h */
+  {18,7,imr,A,0,0},	/* ld.w */
+  {5,0,imr,A,0,0},	/* and */
+  {6,0,imr,A,0,0},	/* or */
+  {7,0,imr,A,0,0},	/* xor */
+  {8,0,imr,A,0,0},	/* shf */
+  {9,6,imr,A,0,0},	/* add.h */
+  {9,7,imr,A,0,0},	/* add.w */
+  {10,6,imr,A,0,0},	/* sub.h */
+  {10,7,imr,A,0,0},	/* sub.w */
+  {3,6,imr,A,0,0},	/* mul.h */
+  {3,7,imr,A,0,0},	/* mul.w */
+  {4,6,imr,A,0,0},	/* div.h */
+  {4,7,imr,A,0,0},	/* div.w */
+  {18,7,iml,VL,0,0},	/* ld.w */
+  {18,7,iml,VS,0,0},	/* ld.w */
+  {0,0,0,0,0,0},
+  {8,7,imr,S,0,0},	/* shf.w */
+  {93,0,a5,0,0,0},	/* trap */
+  {0,0,0,0,0,0},
+  {37,6,imr,A,0,0},	/* eq.h */
+  {37,7,imr,A,0,0},	/* eq.w */
+  {38,6,imr,A,0,0},	/* leu.h */
+  {38,7,imr,A,0,0},	/* leu.w */
+  {39,6,imr,A,0,0},	/* ltu.h */
+  {39,7,imr,A,0,0},	/* ltu.w */
+  {40,6,imr,A,0,0},	/* le.h */
+  {40,7,imr,A,0,0},	/* le.w */
+  {41,6,imr,A,0,0},	/* lt.h */
+  {41,7,imr,A,0,0},	/* lt.w */
+};
+
+CONST struct formstr format1b[] = {
+  {18,4,imr,S,0,0},	/* ld.d */
+  {18,10,imr,S,0,0},	/* ld.u */
+  {18,8,imr,S,0,0},	/* ld.l */
+  {18,7,imr,S,0,0},	/* ld.w */
+  {5,0,imr,S,0,0},	/* and */
+  {6,0,imr,S,0,0},	/* or */
+  {7,0,imr,S,0,0},	/* xor */
+  {8,0,imr,S,0,0},	/* shf */
+  {9,6,imr,S,0,0},	/* add.h */
+  {9,7,imr,S,0,0},	/* add.w */
+  {10,6,imr,S,0,0},	/* sub.h */
+  {10,7,imr,S,0,0},	/* sub.w */
+  {3,6,imr,S,0,0},	/* mul.h */
+  {3,7,imr,S,0,0},	/* mul.w */
+  {4,6,imr,S,0,0},	/* div.h */
+  {4,7,imr,S,0,0},	/* div.w */
+  {9,3,imr,S,0,0},	/* add.s */
+  {10,3,imr,S,0,0},	/* sub.s */
+  {3,3,imr,S,0,0},	/* mul.s */
+  {4,3,imr,S,0,0},	/* div.s */
+  {40,3,imr,S,0,0},	/* le.s */
+  {41,3,imr,S,0,0},	/* lt.s */
+  {37,6,imr,S,0,0},	/* eq.h */
+  {37,7,imr,S,0,0},	/* eq.w */
+  {38,6,imr,S,0,0},	/* leu.h */
+  {38,7,imr,S,0,0},	/* leu.w */
+  {39,6,imr,S,0,0},	/* ltu.h */
+  {39,7,imr,S,0,0},	/* ltu.w */
+  {40,6,imr,S,0,0},	/* le.h */
+  {40,7,imr,S,0,0},	/* le.w */
+  {41,6,imr,S,0,0},	/* lt.h */
+  {41,7,imr,S,0,0},	/* lt.w */
+};
+
+CONST struct formstr e0_format0[] = {
+  {10,3,rrr,S,V,V},	/* sub.s */
+  {10,4,rrr,S,V,V},	/* sub.d */
+  {4,3,rrr,S,V,V},	/* div.s */
+  {4,4,rrr,S,V,V},	/* div.d */
+  {10,11,rrr,S,V,V},	/* sub.s.f */
+  {10,12,rrr,S,V,V},	/* sub.d.f */
+  {4,11,rrr,S,V,V},	/* div.s.f */
+  {4,12,rrr,S,V,V},	/* div.d.f */
+  {3,11,rrr,V,V,V},	/* mul.s.f */
+  {3,12,rrr,V,V,V},	/* mul.d.f */
+  {4,11,rrr,V,V,V},	/* div.s.f */
+  {4,12,rrr,V,V,V},	/* div.d.f */
+  {3,11,rrr,V,S,V},	/* mul.s.f */
+  {3,12,rrr,V,S,V},	/* mul.d.f */
+  {4,11,rrr,V,S,V},	/* div.s.f */
+  {4,12,rrr,V,S,V},	/* div.d.f */
+  {5,2,rrr,V,V,V},	/* and.f */
+  {6,2,rrr,V,V,V},	/* or.f */
+  {7,2,rrr,V,V,V},	/* xor.f */
+  {8,2,rrr,V,V,V},	/* shf.f */
+  {5,2,rrr,V,S,V},	/* and.f */
+  {6,2,rrr,V,S,V},	/* or.f */
+  {7,2,rrr,V,S,V},	/* xor.f */
+  {8,2,rrr,V,S,V},	/* shf.f */
+  {9,11,rrr,V,V,V},	/* add.s.f */
+  {9,12,rrr,V,V,V},	/* add.d.f */
+  {10,11,rrr,V,V,V},	/* sub.s.f */
+  {10,12,rrr,V,V,V},	/* sub.d.f */
+  {9,11,rrr,V,S,V},	/* add.s.f */
+  {9,12,rrr,V,S,V},	/* add.d.f */
+  {10,11,rrr,V,S,V},	/* sub.s.f */
+  {10,12,rrr,V,S,V},	/* sub.d.f */
+  {9,13,rrr,V,V,V},	/* add.b.f */
+  {9,14,rrr,V,V,V},	/* add.h.f */
+  {9,15,rrr,V,V,V},	/* add.w.f */
+  {9,16,rrr,V,V,V},	/* add.l.f */
+  {9,13,rrr,V,S,V},	/* add.b.f */
+  {9,14,rrr,V,S,V},	/* add.h.f */
+  {9,15,rrr,V,S,V},	/* add.w.f */
+  {9,16,rrr,V,S,V},	/* add.l.f */
+  {10,13,rrr,V,V,V},	/* sub.b.f */
+  {10,14,rrr,V,V,V},	/* sub.h.f */
+  {10,15,rrr,V,V,V},	/* sub.w.f */
+  {10,16,rrr,V,V,V},	/* sub.l.f */
+  {10,13,rrr,V,S,V},	/* sub.b.f */
+  {10,14,rrr,V,S,V},	/* sub.h.f */
+  {10,15,rrr,V,S,V},	/* sub.w.f */
+  {10,16,rrr,V,S,V},	/* sub.l.f */
+  {3,13,rrr,V,V,V},	/* mul.b.f */
+  {3,14,rrr,V,V,V},	/* mul.h.f */
+  {3,15,rrr,V,V,V},	/* mul.w.f */
+  {3,16,rrr,V,V,V},	/* mul.l.f */
+  {3,13,rrr,V,S,V},	/* mul.b.f */
+  {3,14,rrr,V,S,V},	/* mul.h.f */
+  {3,15,rrr,V,S,V},	/* mul.w.f */
+  {3,16,rrr,V,S,V},	/* mul.l.f */
+  {4,13,rrr,V,V,V},	/* div.b.f */
+  {4,14,rrr,V,V,V},	/* div.h.f */
+  {4,15,rrr,V,V,V},	/* div.w.f */
+  {4,16,rrr,V,V,V},	/* div.l.f */
+  {4,13,rrr,V,S,V},	/* div.b.f */
+  {4,14,rrr,V,S,V},	/* div.h.f */
+  {4,15,rrr,V,S,V},	/* div.w.f */
+  {4,16,rrr,V,S,V},	/* div.l.f */
+};
+
+CONST struct formstr e0_format1[] = {
+  {0,0,0,0,0,0},
+  {94,0,a3,0,0,0},	/* tst */
+  {95,0,a3,0,0,0},	/* lck */
+  {96,0,a3,0,0,0},	/* ulk */
+  {17,0,a1r,S,0,0},	/* ldea */
+  {97,0,a1r,A,0,0},	/* spawn */
+  {98,0,a1r,A,0,0},	/* ldcmr */
+  {99,0,a2r,A,0,0},	/* stcmr */
+  {100,0,a1r,A,0,0},	/* popr */
+  {101,0,a2r,A,0,0},	/* pshr */
+  {102,7,a1r,A,0,0},	/* rcvr.w */
+  {103,7,a2r,A,0,0},	/* matm.w */
+  {104,7,a2r,A,0,0},	/* sndr.w */
+  {104,8,a2r,S,0,0},	/* sndr.l */
+  {102,8,a1r,S,0,0},	/* rcvr.l */
+  {103,8,a2r,S,0,0},	/* matm.l */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {105,7,a2r,A,0,0},	/* putr.w */
+  {105,8,a2r,S,0,0},	/* putr.l */
+  {106,7,a1r,A,0,0},	/* getr.w */
+  {106,8,a1r,S,0,0},	/* getr.l */
+  {26,13,a2r,S,0,0},	/* ste.b.f */
+  {26,14,a2r,S,0,0},	/* ste.h.f */
+  {26,15,a2r,S,0,0},	/* ste.w.f */
+  {26,16,a2r,S,0,0},	/* ste.l.f */
+  {107,7,a2r,A,0,0},	/* matr.w */
+  {108,7,a2r,A,0,0},	/* mat.w */
+  {109,7,a1r,A,0,0},	/* get.w */
+  {110,7,a1r,A,0,0},	/* rcv.w */
+  {0,0,0,0,0,0},
+  {111,7,a1r,A,0,0},	/* inc.w */
+  {112,7,a2r,A,0,0},	/* put.w */
+  {113,7,a2r,A,0,0},	/* snd.w */
+  {107,8,a2r,S,0,0},	/* matr.l */
+  {108,8,a2r,S,0,0},	/* mat.l */
+  {109,8,a1r,S,0,0},	/* get.l */
+  {110,8,a1r,S,0,0},	/* rcv.l */
+  {0,0,0,0,0,0},
+  {111,8,a1r,S,0,0},	/* inc.l */
+  {112,8,a2r,S,0,0},	/* put.l */
+  {113,8,a2r,S,0,0},	/* snd.l */
+  {18,13,a1r,V,0,0},	/* ld.b.f */
+  {18,14,a1r,V,0,0},	/* ld.h.f */
+  {18,15,a1r,V,0,0},	/* ld.w.f */
+  {18,16,a1r,V,0,0},	/* ld.l.f */
+  {21,13,a2r,V,0,0},	/* st.b.f */
+  {21,14,a2r,V,0,0},	/* st.h.f */
+  {21,15,a2r,V,0,0},	/* st.w.f */
+  {21,16,a2r,V,0,0},	/* st.l.f */
+};
+
+CONST struct formstr e0_format2[] = {
+  {28,5,rr,V,V,0},	/* cvtw.b */
+  {28,6,rr,V,V,0},	/* cvtw.h */
+  {29,7,rr,V,V,0},	/* cvtb.w */
+  {30,7,rr,V,V,0},	/* cvth.w */
+  {28,13,rr,V,V,0},	/* cvtw.b.f */
+  {28,14,rr,V,V,0},	/* cvtw.h.f */
+  {29,15,rr,V,V,0},	/* cvtb.w.f */
+  {30,15,rr,V,V,0},	/* cvth.w.f */
+  {31,8,rr,V,V,0},	/* cvts.l */
+  {32,7,rr,V,V,0},	/* cvtd.w */
+  {33,3,rr,V,V,0},	/* cvtl.s */
+  {28,4,rr,V,V,0},	/* cvtw.d */
+  {31,16,rr,V,V,0},	/* cvts.l.f */
+  {32,15,rr,V,V,0},	/* cvtd.w.f */
+  {33,11,rr,V,V,0},	/* cvtl.s.f */
+  {28,12,rr,V,V,0},	/* cvtw.d.f */
+  {114,0,rr,S,S,0},	/* enal */
+  {8,7,rr,S,S,0},	/* shf.w */
+  {115,0,rr,S,S,0},	/* enag */
+  {0,0,0,0,0,0},
+  {28,4,rr,S,S,0},	/* cvtw.d */
+  {32,7,rr,S,S,0},	/* cvtd.w */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,3,rr,S,S,0},	/* frint.s */
+  {116,4,rr,S,S,0},	/* frint.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,3,rr,V,V,0},	/* frint.s */
+  {116,4,rr,V,V,0},	/* frint.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,11,rr,V,V,0},	/* frint.s.f */
+  {116,12,rr,V,V,0},	/* frint.d.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {81,3,rr,V,V,0},	/* sqrt.s */
+  {81,4,rr,V,V,0},	/* sqrt.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {81,11,rr,V,V,0},	/* sqrt.s.f */
+  {81,12,rr,V,V,0},	/* sqrt.d.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e0_format3[] = {
+  {32,11,rr,V,V,0},	/* cvtd.s.f */
+  {31,12,rr,V,V,0},	/* cvts.d.f */
+  {33,12,rr,V,V,0},	/* cvtl.d.f */
+  {32,16,rr,V,V,0},	/* cvtd.l.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {36,2,rr,V,V,0},	/* tzc.f */
+  {44,2,rr,V,V,0},	/* lop.f */
+  {117,2,rr,V,V,0},	/* xpnd.f */
+  {42,2,rr,V,V,0},	/* not.f */
+  {8,2,rr,S,V,0},	/* shf.f */
+  {35,17,rr,V,V,0},	/* plc.t.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {37,11,rr,V,V,0},	/* eq.s.f */
+  {37,12,rr,V,V,0},	/* eq.d.f */
+  {43,11,rr,V,V,0},	/* neg.s.f */
+  {43,12,rr,V,V,0},	/* neg.d.f */
+  {37,11,rr,S,V,0},	/* eq.s.f */
+  {37,12,rr,S,V,0},	/* eq.d.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {40,11,rr,V,V,0},	/* le.s.f */
+  {40,12,rr,V,V,0},	/* le.d.f */
+  {41,11,rr,V,V,0},	/* lt.s.f */
+  {41,12,rr,V,V,0},	/* lt.d.f */
+  {40,11,rr,S,V,0},	/* le.s.f */
+  {40,12,rr,S,V,0},	/* le.d.f */
+  {41,11,rr,S,V,0},	/* lt.s.f */
+  {41,12,rr,S,V,0},	/* lt.d.f */
+  {37,13,rr,V,V,0},	/* eq.b.f */
+  {37,14,rr,V,V,0},	/* eq.h.f */
+  {37,15,rr,V,V,0},	/* eq.w.f */
+  {37,16,rr,V,V,0},	/* eq.l.f */
+  {37,13,rr,S,V,0},	/* eq.b.f */
+  {37,14,rr,S,V,0},	/* eq.h.f */
+  {37,15,rr,S,V,0},	/* eq.w.f */
+  {37,16,rr,S,V,0},	/* eq.l.f */
+  {40,13,rr,V,V,0},	/* le.b.f */
+  {40,14,rr,V,V,0},	/* le.h.f */
+  {40,15,rr,V,V,0},	/* le.w.f */
+  {40,16,rr,V,V,0},	/* le.l.f */
+  {40,13,rr,S,V,0},	/* le.b.f */
+  {40,14,rr,S,V,0},	/* le.h.f */
+  {40,15,rr,S,V,0},	/* le.w.f */
+  {40,16,rr,S,V,0},	/* le.l.f */
+  {41,13,rr,V,V,0},	/* lt.b.f */
+  {41,14,rr,V,V,0},	/* lt.h.f */
+  {41,15,rr,V,V,0},	/* lt.w.f */
+  {41,16,rr,V,V,0},	/* lt.l.f */
+  {41,13,rr,S,V,0},	/* lt.b.f */
+  {41,14,rr,S,V,0},	/* lt.h.f */
+  {41,15,rr,S,V,0},	/* lt.w.f */
+  {41,16,rr,S,V,0},	/* lt.l.f */
+  {43,13,rr,V,V,0},	/* neg.b.f */
+  {43,14,rr,V,V,0},	/* neg.h.f */
+  {43,15,rr,V,V,0},	/* neg.w.f */
+  {43,16,rr,V,V,0},	/* neg.l.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e0_format4[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e0_format5[] = {
+  {51,13,rr,V,V,0},	/* ldvi.b.f */
+  {51,14,rr,V,V,0},	/* ldvi.h.f */
+  {51,15,rr,V,V,0},	/* ldvi.w.f */
+  {51,16,rr,V,V,0},	/* ldvi.l.f */
+  {28,11,rr,V,V,0},	/* cvtw.s.f */
+  {31,15,rr,V,V,0},	/* cvts.w.f */
+  {28,16,rr,V,V,0},	/* cvtw.l.f */
+  {33,15,rr,V,V,0},	/* cvtl.w.f */
+  {52,13,rxr,V,V,0},	/* stvi.b.f */
+  {52,14,rxr,V,V,0},	/* stvi.h.f */
+  {52,15,rxr,V,V,0},	/* stvi.w.f */
+  {52,16,rxr,V,V,0},	/* stvi.l.f */
+  {52,13,rxr,S,V,0},	/* stvi.b.f */
+  {52,14,rxr,S,V,0},	/* stvi.h.f */
+  {52,15,rxr,S,V,0},	/* stvi.w.f */
+  {52,16,rxr,S,V,0},	/* stvi.l.f */
+};
+
+CONST struct formstr e0_format6[] = {
+  {0,0,rxl,S,CIR,0},	/* mov */
+  {0,0,lr,CIR,S,0},	/* mov */
+  {0,0,lr,TOC,S,0},	/* mov */
+  {0,0,lr,CPUID,S,0},	/* mov */
+  {0,0,rxl,S,TTR,0},	/* mov */
+  {0,0,lr,TTR,S,0},	/* mov */
+  {118,0,nops,0,0,0},	/* ctrsl */
+  {119,0,nops,0,0,0},	/* ctrsg */
+  {0,0,rxl,S,VMU,0},	/* mov */
+  {0,0,lr,VMU,S,0},	/* mov */
+  {0,0,rxl,S,VML,0},	/* mov */
+  {0,0,lr,VML,S,0},	/* mov */
+  {0,0,rxl,S,ICR,0},	/* mov */
+  {0,0,lr,ICR,S,0},	/* mov */
+  {0,0,rxl,S,TCPU,0},	/* mov */
+  {0,0,lr,TCPU,S,0},	/* mov */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {120,0,nops,0,0,0},	/* stop */
+  {0,0,0,0,0,0},
+  {0,0,rxl,S,TID,0},	/* mov */
+  {0,0,lr,TID,S,0},	/* mov */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e0_format7[] = {
+  {84,13,r,V,0,0},	/* sum.b.f */
+  {84,14,r,V,0,0},	/* sum.h.f */
+  {84,15,r,V,0,0},	/* sum.w.f */
+  {84,16,r,V,0,0},	/* sum.l.f */
+  {85,2,r,V,0,0},	/* all.f */
+  {86,2,r,V,0,0},	/* any.f */
+  {87,2,r,V,0,0},	/* parity.f */
+  {0,0,0,0,0,0},
+  {88,13,r,V,0,0},	/* max.b.f */
+  {88,14,r,V,0,0},	/* max.h.f */
+  {88,15,r,V,0,0},	/* max.w.f */
+  {88,16,r,V,0,0},	/* max.l.f */
+  {89,13,r,V,0,0},	/* min.b.f */
+  {89,14,r,V,0,0},	/* min.h.f */
+  {89,15,r,V,0,0},	/* min.w.f */
+  {89,16,r,V,0,0},	/* min.l.f */
+  {84,11,r,V,0,0},	/* sum.s.f */
+  {84,12,r,V,0,0},	/* sum.d.f */
+  {90,11,r,V,0,0},	/* prod.s.f */
+  {90,12,r,V,0,0},	/* prod.d.f */
+  {88,11,r,V,0,0},	/* max.s.f */
+  {88,12,r,V,0,0},	/* max.d.f */
+  {89,11,r,V,0,0},	/* min.s.f */
+  {89,12,r,V,0,0},	/* min.d.f */
+  {90,13,r,V,0,0},	/* prod.b.f */
+  {90,14,r,V,0,0},	/* prod.h.f */
+  {90,15,r,V,0,0},	/* prod.w.f */
+  {90,16,r,V,0,0},	/* prod.l.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e1_format0[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {10,18,rrr,S,V,V},	/* sub.s.t */
+  {10,19,rrr,S,V,V},	/* sub.d.t */
+  {4,18,rrr,S,V,V},	/* div.s.t */
+  {4,19,rrr,S,V,V},	/* div.d.t */
+  {3,18,rrr,V,V,V},	/* mul.s.t */
+  {3,19,rrr,V,V,V},	/* mul.d.t */
+  {4,18,rrr,V,V,V},	/* div.s.t */
+  {4,19,rrr,V,V,V},	/* div.d.t */
+  {3,18,rrr,V,S,V},	/* mul.s.t */
+  {3,19,rrr,V,S,V},	/* mul.d.t */
+  {4,18,rrr,V,S,V},	/* div.s.t */
+  {4,19,rrr,V,S,V},	/* div.d.t */
+  {5,1,rrr,V,V,V},	/* and.t */
+  {6,1,rrr,V,V,V},	/* or.t */
+  {7,1,rrr,V,V,V},	/* xor.t */
+  {8,1,rrr,V,V,V},	/* shf.t */
+  {5,1,rrr,V,S,V},	/* and.t */
+  {6,1,rrr,V,S,V},	/* or.t */
+  {7,1,rrr,V,S,V},	/* xor.t */
+  {8,1,rrr,V,S,V},	/* shf.t */
+  {9,18,rrr,V,V,V},	/* add.s.t */
+  {9,19,rrr,V,V,V},	/* add.d.t */
+  {10,18,rrr,V,V,V},	/* sub.s.t */
+  {10,19,rrr,V,V,V},	/* sub.d.t */
+  {9,18,rrr,V,S,V},	/* add.s.t */
+  {9,19,rrr,V,S,V},	/* add.d.t */
+  {10,18,rrr,V,S,V},	/* sub.s.t */
+  {10,19,rrr,V,S,V},	/* sub.d.t */
+  {9,20,rrr,V,V,V},	/* add.b.t */
+  {9,21,rrr,V,V,V},	/* add.h.t */
+  {9,22,rrr,V,V,V},	/* add.w.t */
+  {9,23,rrr,V,V,V},	/* add.l.t */
+  {9,20,rrr,V,S,V},	/* add.b.t */
+  {9,21,rrr,V,S,V},	/* add.h.t */
+  {9,22,rrr,V,S,V},	/* add.w.t */
+  {9,23,rrr,V,S,V},	/* add.l.t */
+  {10,20,rrr,V,V,V},	/* sub.b.t */
+  {10,21,rrr,V,V,V},	/* sub.h.t */
+  {10,22,rrr,V,V,V},	/* sub.w.t */
+  {10,23,rrr,V,V,V},	/* sub.l.t */
+  {10,20,rrr,V,S,V},	/* sub.b.t */
+  {10,21,rrr,V,S,V},	/* sub.h.t */
+  {10,22,rrr,V,S,V},	/* sub.w.t */
+  {10,23,rrr,V,S,V},	/* sub.l.t */
+  {3,20,rrr,V,V,V},	/* mul.b.t */
+  {3,21,rrr,V,V,V},	/* mul.h.t */
+  {3,22,rrr,V,V,V},	/* mul.w.t */
+  {3,23,rrr,V,V,V},	/* mul.l.t */
+  {3,20,rrr,V,S,V},	/* mul.b.t */
+  {3,21,rrr,V,S,V},	/* mul.h.t */
+  {3,22,rrr,V,S,V},	/* mul.w.t */
+  {3,23,rrr,V,S,V},	/* mul.l.t */
+  {4,20,rrr,V,V,V},	/* div.b.t */
+  {4,21,rrr,V,V,V},	/* div.h.t */
+  {4,22,rrr,V,V,V},	/* div.w.t */
+  {4,23,rrr,V,V,V},	/* div.l.t */
+  {4,20,rrr,V,S,V},	/* div.b.t */
+  {4,21,rrr,V,S,V},	/* div.h.t */
+  {4,22,rrr,V,S,V},	/* div.w.t */
+  {4,23,rrr,V,S,V},	/* div.l.t */
+};
+
+CONST struct formstr e1_format1[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {26,20,a2r,S,0,0},	/* ste.b.t */
+  {26,21,a2r,S,0,0},	/* ste.h.t */
+  {26,22,a2r,S,0,0},	/* ste.w.t */
+  {26,23,a2r,S,0,0},	/* ste.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {18,20,a1r,V,0,0},	/* ld.b.t */
+  {18,21,a1r,V,0,0},	/* ld.h.t */
+  {18,22,a1r,V,0,0},	/* ld.w.t */
+  {18,23,a1r,V,0,0},	/* ld.l.t */
+  {21,20,a2r,V,0,0},	/* st.b.t */
+  {21,21,a2r,V,0,0},	/* st.h.t */
+  {21,22,a2r,V,0,0},	/* st.w.t */
+  {21,23,a2r,V,0,0},	/* st.l.t */
+};
+
+CONST struct formstr e1_format2[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {28,20,rr,V,V,0},	/* cvtw.b.t */
+  {28,21,rr,V,V,0},	/* cvtw.h.t */
+  {29,22,rr,V,V,0},	/* cvtb.w.t */
+  {30,22,rr,V,V,0},	/* cvth.w.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {31,23,rr,V,V,0},	/* cvts.l.t */
+  {32,22,rr,V,V,0},	/* cvtd.w.t */
+  {33,18,rr,V,V,0},	/* cvtl.s.t */
+  {28,19,rr,V,V,0},	/* cvtw.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,18,rr,V,V,0},	/* frint.s.t */
+  {116,19,rr,V,V,0},	/* frint.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {81,18,rr,V,V,0},	/* sqrt.s.t */
+  {81,19,rr,V,V,0},	/* sqrt.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e1_format3[] = {
+  {32,18,rr,V,V,0},	/* cvtd.s.t */
+  {31,19,rr,V,V,0},	/* cvts.d.t */
+  {33,19,rr,V,V,0},	/* cvtl.d.t */
+  {32,23,rr,V,V,0},	/* cvtd.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {36,1,rr,V,V,0},	/* tzc.t */
+  {44,1,rr,V,V,0},	/* lop.t */
+  {117,1,rr,V,V,0},	/* xpnd.t */
+  {42,1,rr,V,V,0},	/* not.t */
+  {8,1,rr,S,V,0},	/* shf.t */
+  {35,24,rr,V,V,0},	/* plc.t.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {37,18,rr,V,V,0},	/* eq.s.t */
+  {37,19,rr,V,V,0},	/* eq.d.t */
+  {43,18,rr,V,V,0},	/* neg.s.t */
+  {43,19,rr,V,V,0},	/* neg.d.t */
+  {37,18,rr,S,V,0},	/* eq.s.t */
+  {37,19,rr,S,V,0},	/* eq.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {40,18,rr,V,V,0},	/* le.s.t */
+  {40,19,rr,V,V,0},	/* le.d.t */
+  {41,18,rr,V,V,0},	/* lt.s.t */
+  {41,19,rr,V,V,0},	/* lt.d.t */
+  {40,18,rr,S,V,0},	/* le.s.t */
+  {40,19,rr,S,V,0},	/* le.d.t */
+  {41,18,rr,S,V,0},	/* lt.s.t */
+  {41,19,rr,S,V,0},	/* lt.d.t */
+  {37,20,rr,V,V,0},	/* eq.b.t */
+  {37,21,rr,V,V,0},	/* eq.h.t */
+  {37,22,rr,V,V,0},	/* eq.w.t */
+  {37,23,rr,V,V,0},	/* eq.l.t */
+  {37,20,rr,S,V,0},	/* eq.b.t */
+  {37,21,rr,S,V,0},	/* eq.h.t */
+  {37,22,rr,S,V,0},	/* eq.w.t */
+  {37,23,rr,S,V,0},	/* eq.l.t */
+  {40,20,rr,V,V,0},	/* le.b.t */
+  {40,21,rr,V,V,0},	/* le.h.t */
+  {40,22,rr,V,V,0},	/* le.w.t */
+  {40,23,rr,V,V,0},	/* le.l.t */
+  {40,20,rr,S,V,0},	/* le.b.t */
+  {40,21,rr,S,V,0},	/* le.h.t */
+  {40,22,rr,S,V,0},	/* le.w.t */
+  {40,23,rr,S,V,0},	/* le.l.t */
+  {41,20,rr,V,V,0},	/* lt.b.t */
+  {41,21,rr,V,V,0},	/* lt.h.t */
+  {41,22,rr,V,V,0},	/* lt.w.t */
+  {41,23,rr,V,V,0},	/* lt.l.t */
+  {41,20,rr,S,V,0},	/* lt.b.t */
+  {41,21,rr,S,V,0},	/* lt.h.t */
+  {41,22,rr,S,V,0},	/* lt.w.t */
+  {41,23,rr,S,V,0},	/* lt.l.t */
+  {43,20,rr,V,V,0},	/* neg.b.t */
+  {43,21,rr,V,V,0},	/* neg.h.t */
+  {43,22,rr,V,V,0},	/* neg.w.t */
+  {43,23,rr,V,V,0},	/* neg.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e1_format4[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e1_format5[] = {
+  {51,20,rr,V,V,0},	/* ldvi.b.t */
+  {51,21,rr,V,V,0},	/* ldvi.h.t */
+  {51,22,rr,V,V,0},	/* ldvi.w.t */
+  {51,23,rr,V,V,0},	/* ldvi.l.t */
+  {28,18,rr,V,V,0},	/* cvtw.s.t */
+  {31,22,rr,V,V,0},	/* cvts.w.t */
+  {28,23,rr,V,V,0},	/* cvtw.l.t */
+  {33,22,rr,V,V,0},	/* cvtl.w.t */
+  {52,20,rxr,V,V,0},	/* stvi.b.t */
+  {52,21,rxr,V,V,0},	/* stvi.h.t */
+  {52,22,rxr,V,V,0},	/* stvi.w.t */
+  {52,23,rxr,V,V,0},	/* stvi.l.t */
+  {52,20,rxr,S,V,0},	/* stvi.b.t */
+  {52,21,rxr,S,V,0},	/* stvi.h.t */
+  {52,22,rxr,S,V,0},	/* stvi.w.t */
+  {52,23,rxr,S,V,0},	/* stvi.l.t */
+};
+
+CONST struct formstr e1_format6[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+CONST struct formstr e1_format7[] = {
+  {84,20,r,V,0,0},	/* sum.b.t */
+  {84,21,r,V,0,0},	/* sum.h.t */
+  {84,22,r,V,0,0},	/* sum.w.t */
+  {84,23,r,V,0,0},	/* sum.l.t */
+  {85,1,r,V,0,0},	/* all.t */
+  {86,1,r,V,0,0},	/* any.t */
+  {87,1,r,V,0,0},	/* parity.t */
+  {0,0,0,0,0,0},
+  {88,20,r,V,0,0},	/* max.b.t */
+  {88,21,r,V,0,0},	/* max.h.t */
+  {88,22,r,V,0,0},	/* max.w.t */
+  {88,23,r,V,0,0},	/* max.l.t */
+  {89,20,r,V,0,0},	/* min.b.t */
+  {89,21,r,V,0,0},	/* min.h.t */
+  {89,22,r,V,0,0},	/* min.w.t */
+  {89,23,r,V,0,0},	/* min.l.t */
+  {84,18,r,V,0,0},	/* sum.s.t */
+  {84,19,r,V,0,0},	/* sum.d.t */
+  {90,18,r,V,0,0},	/* prod.s.t */
+  {90,19,r,V,0,0},	/* prod.d.t */
+  {88,18,r,V,0,0},	/* max.s.t */
+  {88,19,r,V,0,0},	/* max.d.t */
+  {89,18,r,V,0,0},	/* min.s.t */
+  {89,19,r,V,0,0},	/* min.d.t */
+  {90,20,r,V,0,0},	/* prod.b.t */
+  {90,21,r,V,0,0},	/* prod.h.t */
+  {90,22,r,V,0,0},	/* prod.w.t */
+  {90,23,r,V,0,0},	/* prod.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+char *lop[] = {
+  "mov",	/* 0 */
+  "merg",	/* 1 */
+  "mask",	/* 2 */
+  "mul",	/* 3 */
+  "div",	/* 4 */
+  "and",	/* 5 */
+  "or",	/* 6 */
+  "xor",	/* 7 */
+  "shf",	/* 8 */
+  "add",	/* 9 */
+  "sub",	/* 10 */
+  "exit",	/* 11 */
+  "jmp",	/* 12 */
+  "jmpi",	/* 13 */
+  "jmpa",	/* 14 */
+  "jmps",	/* 15 */
+  "tac",	/* 16 */
+  "ldea",	/* 17 */
+  "ld",	/* 18 */
+  "tas",	/* 19 */
+  "pshea",	/* 20 */
+  "st",	/* 21 */
+  "call",	/* 22 */
+  "calls",	/* 23 */
+  "callq",	/* 24 */
+  "pfork",	/* 25 */
+  "ste",	/* 26 */
+  "incr",	/* 27 */
+  "cvtw",	/* 28 */
+  "cvtb",	/* 29 */
+  "cvth",	/* 30 */
+  "cvts",	/* 31 */
+  "cvtd",	/* 32 */
+  "cvtl",	/* 33 */
+  "ldpa",	/* 34 */
+  "plc",	/* 35 */
+  "tzc",	/* 36 */
+  "eq",	/* 37 */
+  "leu",	/* 38 */
+  "ltu",	/* 39 */
+  "le",	/* 40 */
+  "lt",	/* 41 */
+  "not",	/* 42 */
+  "neg",	/* 43 */
+  "lop",	/* 44 */
+  "cprs",	/* 45 */
+  "nop",	/* 46 */
+  "br",	/* 47 */
+  "bri",	/* 48 */
+  "bra",	/* 49 */
+  "brs",	/* 50 */
+  "ldvi",	/* 51 */
+  "stvi",	/* 52 */
+  "ldsdr",	/* 53 */
+  "ldkdr",	/* 54 */
+  "ln",	/* 55 */
+  "patu",	/* 56 */
+  "pate",	/* 57 */
+  "pich",	/* 58 */
+  "plch",	/* 59 */
+  "idle",	/* 60 */
+  "rtnq",	/* 61 */
+  "cfork",	/* 62 */
+  "rtn",	/* 63 */
+  "wfork",	/* 64 */
+  "join",	/* 65 */
+  "rtnc",	/* 66 */
+  "exp",	/* 67 */
+  "sin",	/* 68 */
+  "cos",	/* 69 */
+  "psh",	/* 70 */
+  "pop",	/* 71 */
+  "eni",	/* 72 */
+  "dsi",	/* 73 */
+  "bkpt",	/* 74 */
+  "msync",	/* 75 */
+  "mski",	/* 76 */
+  "xmti",	/* 77 */
+  "tstvv",	/* 78 */
+  "diag",	/* 79 */
+  "pbkpt",	/* 80 */
+  "sqrt",	/* 81 */
+  "casr",	/* 82 */
+  "atan",	/* 83 */
+  "sum",	/* 84 */
+  "all",	/* 85 */
+  "any",	/* 86 */
+  "parity",	/* 87 */
+  "max",	/* 88 */
+  "min",	/* 89 */
+  "prod",	/* 90 */
+  "halt",	/* 91 */
+  "sysc",	/* 92 */
+  "trap",	/* 93 */
+  "tst",	/* 94 */
+  "lck",	/* 95 */
+  "ulk",	/* 96 */
+  "spawn",	/* 97 */
+  "ldcmr",	/* 98 */
+  "stcmr",	/* 99 */
+  "popr",	/* 100 */
+  "pshr",	/* 101 */
+  "rcvr",	/* 102 */
+  "matm",	/* 103 */
+  "sndr",	/* 104 */
+  "putr",	/* 105 */
+  "getr",	/* 106 */
+  "matr",	/* 107 */
+  "mat",	/* 108 */
+  "get",	/* 109 */
+  "rcv",	/* 110 */
+  "inc",	/* 111 */
+  "put",	/* 112 */
+  "snd",	/* 113 */
+  "enal",	/* 114 */
+  "enag",	/* 115 */
+  "frint",	/* 116 */
+  "xpnd",	/* 117 */
+  "ctrsl",	/* 118 */
+  "ctrsg",	/* 119 */
+  "stop",	/* 120 */
+};
+
+char *rop[] = {
+  "",	/* 0 */
+  ".t",	/* 1 */
+  ".f",	/* 2 */
+  ".s",	/* 3 */
+  ".d",	/* 4 */
+  ".b",	/* 5 */
+  ".h",	/* 6 */
+  ".w",	/* 7 */
+  ".l",	/* 8 */
+  ".x",	/* 9 */
+  ".u",	/* 10 */
+  ".s.f",	/* 11 */
+  ".d.f",	/* 12 */
+  ".b.f",	/* 13 */
+  ".h.f",	/* 14 */
+  ".w.f",	/* 15 */
+  ".l.f",	/* 16 */
+  ".t.f",	/* 17 */
+  ".s.t",	/* 18 */
+  ".d.t",	/* 19 */
+  ".b.t",	/* 20 */
+  ".h.t",	/* 21 */
+  ".w.t",	/* 22 */
+  ".l.t",	/* 23 */
+  ".t.t",	/* 24 */
+};
diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h
new file mode 100644
index 000000000000..c74d2d6a2701
--- /dev/null
+++ b/contrib/binutils/include/opcode/i386.h
@@ -0,0 +1,981 @@
+/* i386-opcode.h -- Intel 80386 opcode table
+   Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
+
+This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* The NON_BROKEN_OPCODES cases use the operands in the reverse order
+   from that documented in the Intel manuals.  The opcode values are
+   such that they actually generate different instructions.  These
+   values must not be changed, as they are the values generated by the
+   UnixWare assembler, and possibly other ix86 assemblers.  */
+
+static const template i386_optab[] = {
+
+#define _ None
+/* move instructions */
+#define MOV_AX_DISP32 0xa0
+{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } },
+{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
+{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
+{ "mov", 2, 0xc6, _,  W|Modrm,  { Imm, Reg|Mem, 0 } },
+{ "mov", 2, 0x8c, _, D|Modrm,  { SReg3|SReg2, Reg16|Mem, 0 } },
+/* move to/from control debug registers */
+{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
+{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
+{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} },
+
+/* move with sign extend */
+/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
+   conflict with the "movs" string move instruction.  Thus,
+   {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem,  Reg16|Reg32, 0} },
+   is not kosher; we must seperate the two instructions. */
+{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem,  Reg32, 0} },
+{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem,  Reg16, 0} },
+{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
+
+/* move with zero extend */
+{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
+{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
+
+/* push instructions */
+{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } },
+{"push", 1, 0xff, 0x6,  Modrm, { WordReg|WordMem, 0, 0 } },
+{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} },
+{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} },
+{"push", 1, 0x06, _,  Seg2ShortForm, { SReg2,0,0 } },
+{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } },
+/* push all */
+{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } },
+
+/* pop instructions */
+{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } },
+{"pop", 1, 0x8f, 0x0,  Modrm, { WordReg|WordMem, 0, 0 } },
+#define POP_SEG_SHORT 0x7
+{"pop", 1, 0x07, _,  Seg2ShortForm, { SReg2,0,0 } },
+{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } },
+/* pop all */
+{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } },
+
+/* xchg exchange instructions
+   xchg commutes:  we allow both operand orders */
+{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } },
+{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } },
+{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } },
+{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } },
+
+/* in/out from ports */
+{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } },
+{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } },
+{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } },
+{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } },
+{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } },
+{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } },
+{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } },
+{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } },
+
+/* load effective address */
+{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } },
+
+/* load segment registers from memory */
+{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} },
+{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} },
+{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} },
+{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} },
+{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} },
+
+/* flags register instructions */
+{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} },
+{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} },
+{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} },
+{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} },
+{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} },
+{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} },
+{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} },
+{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} },
+{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} },
+{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} },
+{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} },
+{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} },
+{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} },
+{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} },
+{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} },
+{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} },
+
+{"add", 2, 0x0,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"add", 2, 0x83, 0,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"add", 2, 0x4,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} },
+{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"sub", 2, 0x28,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"sub", 2, 0x83, 5,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"sub", 2, 0x2c,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"sub", 2, 0x80, 5,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} },
+{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"sbb", 2, 0x18,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"sbb", 2, 0x83, 3,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"sbb", 2, 0x1c,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"sbb", 2, 0x80, 3,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"cmp", 2, 0x38,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"cmp", 2, 0x83, 7,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"cmp", 2, 0x3c,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"cmp", 2, 0x80, 7,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} },
+{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} },
+{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} },
+{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"and", 2, 0x20,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"and", 2, 0x83, 4,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"and", 2, 0x24,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"and", 2, 0x80, 4,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"or", 2, 0x08,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"or", 2, 0x83, 1,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"or", 2, 0x0c,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"or", 2, 0x80, 1,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"xor", 2, 0x30,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"xor", 2, 0x83, 6,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"xor", 2, 0x34,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"xor", 2, 0x80, 6,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+/* iclr with 1 operand is really xor with 2 operands.  */
+{"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } },
+
+{"adc", 2, 0x10,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
+{"adc", 2, 0x83, 2,  Modrm, { Imm8S, WordReg|WordMem, 0} },
+{"adc", 2, 0x14,  _,  W|NoModrm, { Imm,  Acc,    0} },
+{"adc", 2, 0x80, 2,  W|Modrm, { Imm, Reg|Mem, 0} },
+
+{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
+{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} },
+{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} },
+{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} },
+{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} },
+{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} },
+{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} },
+
+/* conversion insns */
+/* conversion:  intel naming */
+{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
+{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
+{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
+{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
+/*  att naming */
+{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
+{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
+{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
+{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
+
+/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
+   expanding 64-bit multiplies, and *cannot* be selected to accomplish
+   'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
+   These multiplies can only be selected with single operand forms. */
+{"mul",  1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
+{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
+
+
+
+
+/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
+   These instructions are exceptions:  'imul $2, %eax, %ecx' would put
+   '%eax' in the reg field and '%ecx' in the regmem field if we did not
+   switch them. */
+{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
+{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
+{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
+/*
+  imul with 2 operands mimicks imul with 3 by puting register both
+  in i.rm.reg & i.rm.regmem fields
+*/
+{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} },
+{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
+{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
+{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
+{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
+{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
+
+{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
+{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
+{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
+{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} },
+
+{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
+
+{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
+{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
+{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} },
+
+{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
+{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
+{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
+{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
+
+/* control transfer instructions */
+#define CALL_PC_RELATIVE 0xe8
+{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} },
+{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} },
+{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} },
+#define CALL_FAR_IMMEDIATE 0x9a
+{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} },
+{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} },
+{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} },
+
+#define JUMP_PC_RELATIVE 0xeb
+{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} },
+{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
+#define JUMP_FAR_IMMEDIATE 0xea
+{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} },
+{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} },
+
+{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} },
+{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} },
+{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} },
+{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} },
+{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} },
+{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} },
+{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} },
+{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} },
+{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} },
+{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} },
+{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} },
+{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} },
+
+/* conditional jumps */
+{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} },
+
+{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} },
+
+{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} },
+{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} },
+{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} },
+
+{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} },
+{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} },
+{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} },
+
+{"je", 1, 0x74, _, Jump, { Disp, 0, 0} },
+{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} },
+
+{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} },
+{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} },
+
+{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} },
+{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} },
+
+{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} },
+{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} },
+
+{"js", 1, 0x78, _, Jump, { Disp, 0, 0} },
+
+{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} },
+
+{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} },
+{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} },
+
+{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} },
+{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} },
+
+{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} },
+{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} },
+
+{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} },
+{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} },
+
+{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} },
+{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} },
+
+{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
+{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
+
+#if 0  /* XXX where are these macros used?
+	  To get them working again, they need to take
+	  an entire template as the parameter,
+	  and check for Data16/Data32 flags.  */
+/* these turn into pseudo operations when disp is larger than 8 bits */
+#define IS_JUMP_ON_CX_ZERO(o) \
+  (o == 0x66e3)
+#define IS_JUMP_ON_ECX_ZERO(o) \
+  (o == 0xe3)
+#endif
+
+{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} },
+{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} },
+
+#define IS_LOOP_ECX_TIMES(o) \
+  (o == 0xe2 || o == 0xe1 || o == 0xe0)
+
+{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} },
+
+{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
+{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
+
+{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
+{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
+
+/* set byte on flag instructions */
+{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
+{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
+
+#define IS_STRING_INSTRUCTION(o) \
+  ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
+   (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
+   (o) == 0xd7)
+
+/* string manipulation */
+{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
+{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
+{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} },
+{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} },
+{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
+{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
+{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
+{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
+{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
+{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
+{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
+{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
+{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} },
+
+/* bit manipulation */
+{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
+{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
+{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} },
+{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
+{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} },
+{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
+{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} },
+{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
+{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} },
+{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
+
+/* interrupts & op. sys insns */
+/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
+   int 3 insn. */
+#define INT_OPCODE 0xcd
+#define INT3_OPCODE 0xcc
+{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} },
+{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} },
+{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} },
+{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} },
+{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} },
+/* i386sl, i486sl, later 486, and Pentium */
+{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} },
+
+{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} },
+{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} },
+
+{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} },
+{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
+/* nop is actually 'xchgl %eax, %eax' */
+{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} },
+
+/* protection control */
+{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} },
+{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
+{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
+{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
+{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
+{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
+{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
+{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
+
+{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
+{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
+{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
+{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
+{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
+
+{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
+{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
+
+/* floating point instructions */
+
+/* load */
+{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
+{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem float */
+{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem double */
+{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
+{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem word (16) */
+{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} },	/* %st0 <-- mem dword (32) */
+{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem qword (64) */
+{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} },	/* %st0 <-- mem qword (64) */
+{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem efloat */
+{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem bcd */
+
+/* store (no pop) */
+{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
+{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} },		/* %st0 --> mem float */
+{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} },		/* %st0 --> mem double */
+{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
+{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} },		/* %st0 --> mem word (16) */
+{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} },	/* %st0 --> mem dword (32) */
+
+/* store (with pop) */
+{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
+{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem float */
+{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem double */
+{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
+{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem word (16) */
+{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem dword (32) */
+{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} },	/* %st0 --> mem qword (64) */
+{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} },	/* %st0 --> mem qword (64) */
+{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} },	/* %st0 --> mem efloat */
+{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} },	/* %st0 --> mem bcd */
+
+/* exchange %st<n> with %st0 */
+{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} },
+{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
+
+/* comparison (without pop) */
+{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
+{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem float  */
+{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word  */
+{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem double  */
+{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
+{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword */
+
+/* comparison (with pop) */
+{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
+{"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} },   /* fcomp %st, %st(1) */
+{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem float  */
+{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word  */
+{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem double  */
+{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
+{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword */
+{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} },	/* compare %st0, %st1 & pop 2 */
+
+/* unordered comparison (with pop) */
+{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} },
+{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} },
+{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
+
+{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} },	/* test %st0 */
+{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} },	/* examine %st0 */
+
+/* load constants into %st0 */
+{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- 1.0 */
+{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- log2(10) */
+{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- log2(e) */
+{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- pi */
+{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- log10(2) */
+{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- ln(2) */
+{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- 0.0 */
+
+/* arithmetic */
+
+/* add */
+{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} },
+{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
+{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
+{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} },
+{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
+{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
+{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
+{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
+{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
+
+/* sub */
+/* Note:  intel has decided that certain of these operations are reversed
+   in assembler syntax. */
+{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} },
+{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#else
+{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#endif
+{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} },
+{"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} },
+{"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
+#else
+{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
+#endif
+{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
+{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
+{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
+{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
+
+/* sub reverse */
+{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} },
+{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#else
+{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#endif
+{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} },
+{"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} },
+{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
+#else
+{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
+#endif
+{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
+{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
+{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
+{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
+
+/* mul */
+{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} },
+{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
+{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} },
+{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} },
+{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} },
+{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
+{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
+{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
+{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
+
+/* div */
+/* Note:  intel has decided that certain of these operations are reversed
+   in assembler syntax. */
+{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} },
+{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#else
+{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#endif
+{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} },
+{"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} },
+{"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
+#else
+{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
+#endif
+{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
+{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
+{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
+{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
+
+/* div reverse */
+{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} },
+{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#else
+{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+#endif
+{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} },
+{"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} },
+{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+#ifdef NON_BROKEN_OPCODES
+{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
+#else
+{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
+#endif
+{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
+{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
+{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
+{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
+
+{"f2xm1", 0,   0xd9f0, _, NoModrm, { 0, 0, 0} },
+{"fyl2x", 0,   0xd9f1, _, NoModrm, { 0, 0, 0} },
+{"fptan", 0,   0xd9f2, _, NoModrm, { 0, 0, 0} },
+{"fpatan", 0,  0xd9f3, _, NoModrm, { 0, 0, 0} },
+{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} },
+{"fprem1", 0,  0xd9f5, _, NoModrm, { 0, 0, 0} },
+{"fdecstp", 0,  0xd9f6, _, NoModrm, { 0, 0, 0} },
+{"fincstp", 0,  0xd9f7, _, NoModrm, { 0, 0, 0} },
+{"fprem", 0,   0xd9f8, _, NoModrm, { 0, 0, 0} },
+{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} },
+{"fsqrt", 0,   0xd9fa, _, NoModrm, { 0, 0, 0} },
+{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} },
+{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} },
+{"fscale", 0,  0xd9fd, _, NoModrm, { 0, 0, 0} },
+{"fsin", 0,    0xd9fe, _, NoModrm, { 0, 0, 0} },
+{"fcos", 0,    0xd9ff, _, NoModrm, { 0, 0, 0} },
+
+{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} },
+{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
+
+/* processor control */
+{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
+{"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} },
+{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
+{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
+{"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} },
+{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
+{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
+{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
+{"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} },
+{"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} },
+{"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} },
+{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
+{"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} },
+/*
+ We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
+ instructions;  i'm not sure how to add them or how they are different.
+ My 386/387 book offers no details about this.
+*/
+{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
+{"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} },
+{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
+{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
+{"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} },
+{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
+
+{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
+/* P6:free st(i), pop st */
+{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} },
+{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
+{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
+
+/*
+  opcode prefixes; we allow them as seperate insns too
+  (see prefix table below)
+*/
+{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} },
+{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} },
+{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} },
+{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} },
+{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} },
+{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} },
+{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} },
+{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} },
+{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} },
+{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} },
+{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} },
+{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
+{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
+{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
+{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
+{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
+
+/* 486 extensions */
+
+{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } },
+{"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } },
+{"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } },
+{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} },
+{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} },
+{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
+
+/* 586 and late 486 extensions */
+{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} },
+
+/* Pentium extensions */
+{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} },
+{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} },
+{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} },
+{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} },
+
+/* Pentium Pro extensions */
+{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} },
+
+{"ud2", 0, 0x0fff, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */
+
+{"cmovo",  2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovb",  2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmove",  2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmova",  2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovs",  2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovp",  2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovl",  2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+{"cmovg",  2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
+
+{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+
+{"fcomi",  2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} },
+{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
+
+/* MMX instructions.  */
+
+{"emms",      0, 0x0f77, _, NoModrm, { 0, 0, 0 } },
+{"movd",      2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } },
+{"movd",      2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } },
+{"movq",      2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"movq",      2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } },
+{"packssdw",  2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"packsswb",  2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"packuswb",  2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddb",     2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddw",     2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddd",     2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddsb",    2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddsw",    2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddusb",   2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"paddusw",   2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pand",      2, 0x0fda, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pandn",     2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pcmpeqb",   2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pcmpeqw",   2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pcmpeqd",   2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pcmpgtb",   2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pcmpgtw",   2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pcmpgtd",   2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pmaddwd",   2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pmulhw",    2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pmullw",    2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"por",       2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psllw",     2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psllw",     2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } },
+{"pslld",     2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pslld",     2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } },
+{"psllq",     2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psllq",     2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } },
+{"psraw",     2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psraw",     2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } },
+{"psrad",     2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psrad",     2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } },
+{"psrlw",     2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psrlw",     2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } },
+{"psrld",     2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psrld",     2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } },
+{"psrlq",     2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psrlq",     2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } },
+{"psubb",     2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psubw",     2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psubd",     2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psubsb",    2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psubsw",    2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psubusb",   2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"psubusw",   2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pxor",      2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+
+{"", 0, 0, 0, 0, { 0, 0, 0} }	/* sentinel */
+};
+#undef _
+
+static const template *const i386_optab_end
+  = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
+
+/* 386 register table */
+
+static const reg_entry i386_regtab[] = {
+  /* 8 bit regs */
+  {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
+  {"bl", Reg8, 3},
+  {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
+  /* 16 bit regs */
+  {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
+  {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
+  /* 32 bit regs */
+  {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
+  {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
+  /* segment registers */
+  {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
+  {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
+  /* control registers */
+  {"cr0", Control, 0},   {"cr2", Control, 2},   {"cr3", Control, 3},
+  {"cr4", Control, 4},
+  /* debug registers */
+  {"db0", Debug, 0},   {"db1", Debug, 1},   {"db2", Debug, 2},
+  {"db3", Debug, 3},   {"db6", Debug, 6},   {"db7", Debug, 7},
+  {"dr0", Debug, 0},   {"dr1", Debug, 1},   {"dr2", Debug, 2},
+  {"dr3", Debug, 3},   {"dr6", Debug, 6},   {"dr7", Debug, 7},
+  /* test registers */
+  {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5},
+  {"tr6", Test, 6}, {"tr7", Test, 7},
+  /* float registers */
+  {"st(0)", FloatReg|FloatAcc, 0},
+  {"st", FloatReg|FloatAcc, 0},
+  {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
+  {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
+  {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7},
+  {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2},
+  {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5},
+  {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7}
+};
+
+#define MAX_REG_NAME_SIZE 8	/* for parsing register names from input */
+
+static const reg_entry *const i386_regtab_end
+  = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
+
+/* segment stuff */
+static const seg_entry cs = { "cs", 0x2e };
+static const seg_entry ds = { "ds", 0x3e };
+static const seg_entry ss = { "ss", 0x36 };
+static const seg_entry es = { "es", 0x26 };
+static const seg_entry fs = { "fs", 0x64 };
+static const seg_entry gs = { "gs", 0x65 };
+static const seg_entry null = { "", 0x0 };
+
+/*
+  This table is used to store the default segment register implied by all
+  possible memory addressing modes.
+  It is indexed by the mode & modrm entries of the modrm byte as follows:
+      index = (mode<<3) | modrm;
+*/
+static const seg_entry *const one_byte_segment_defaults[] = {
+  /* mode 0 */
+  &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
+  /* mode 1 */
+  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
+  /* mode 2 */
+  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
+  /* mode 3 --- not a memory reference; never referenced */
+};
+
+static const seg_entry *const two_byte_segment_defaults[] = {
+  /* mode 0 */
+  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  /* mode 1 */
+  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  /* mode 2 */
+  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  /* mode 3 --- not a memory reference; never referenced */
+};
+
+static const prefix_entry i386_prefixtab[] = {
+#define ADDR_PREFIX_OPCODE 0x67
+  { "addr16", 0x67 },		/* address size prefix ==> 16bit addressing
+				 * (How is this useful?) */
+#define WORD_PREFIX_OPCODE 0x66
+  { "data16", 0x66 },		/* operand size prefix */
+  { "lock", 0xf0 },		/* bus lock prefix */
+  { "wait", 0x9b },		/* wait for coprocessor */
+  { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
+  { "es", 0x26 }, { "fs", 0x64 },
+  { "gs", 0x65 }, { "ss", 0x36 },
+/* REPE & REPNE used to detect rep/repne with a non-string instruction */
+#define REPNE 0xf2
+#define REPE  0xf3
+  { "rep", 0xf3 }, 		/* repeat string instructions */
+  { "repe", 0xf3 },  { "repz", 0xf3 },
+  { "repne", 0xf2 }, { "repnz", 0xf2 }
+};
+
+static const prefix_entry *const i386_prefixtab_end
+  = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
+
+/* end of i386-opcode.h */
diff --git a/contrib/binutils/include/opcode/np1.h b/contrib/binutils/include/opcode/np1.h
new file mode 100644
index 000000000000..d23adc7566cf
--- /dev/null
+++ b/contrib/binutils/include/opcode/np1.h
@@ -0,0 +1,422 @@
+/* Print GOULD NPL instructions for GDB, the GNU debugger.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+struct gld_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long mask;
+  char *args;
+  int length;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and at most four.  The length of the
+   instruction is based on the opcode.
+
+   The mask component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing characters
+   that are used to format the arguments to the instruction. */
+
+/* Kinds of operands:
+   r  Register in first field
+   R  Register in second field
+   b  Base register in first field
+   B  Base register in second field
+   v  Vector register in first field
+   V  Vector register in first field
+   A  Optional address register (base register)
+   X  Optional index register
+   I  Immediate data (16bits signed)
+   O  Offset field (16bits signed)
+   h  Offset field (15bits signed)
+   d  Offset field (14bits signed)
+   S  Shift count field
+
+   any other characters are printed as is...
+*/
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+struct gld_opcode gld_opcodes[] =
+{
+{ "lb",		0xb4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lbs",	0xec080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lh",		0xb4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lnh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lw",		0xb4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ld",		0xb4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lnd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "li",		0xf8000000,	0xfc7f0000,	"r,I",		4 },
+{ "lpa",	0x50080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "la",		0x50000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "labr",	0x58080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lbp",	0x90080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lhp",	0x90000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lwp",	0x90000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ldp",	0x90000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "suabr",	0x58000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lf",		0xbc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lfbr",	0xbc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lwbr",	0x5c000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "stb",	0xd4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sth",	0xd4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stw",	0xd4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "std",	0xd4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stf",	0xdc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stfbr",	0xdc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "stwbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "zmb",	0xd8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmh",	0xd8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "zmw",	0xd8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmd",	0xd8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stbp",	0x94080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sthp",	0x94000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stwp",	0x94000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stdp",	0x94000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lil",	0xf80b0000,	0xfc7f0000,	"r,D",		4 },
+{ "lwsl1",	0xec000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwsl2",	0xfc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwsl3",	0xfc080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "lvb",	0xb0080000,	0xfc080000,	"v,xOA,X",	4 },
+{ "lvh",	0xb0000001,	0xfc080001,	"v,xOA,X",	4 },
+{ "lvw",	0xb0000000,	0xfc080000,	"v,xOA,X",	4 },
+{ "lvd",	0xb0000002,	0xfc080002,	"v,xOA,X",	4 },
+{ "liv",	0x3c040000,	0xfc0f0000,	"v,R",		2 },
+{ "livf",	0x3c080000,	0xfc0f0000,	"v,R",		2 },
+{ "stvb",	0xd0080000,	0xfc080000,	"v,xOA,X",	4 },
+{ "stvh",	0xd0000001,	0xfc080001,	"v,xOA,X",	4 },
+{ "stvw",	0xd0000000,	0xfc080000,	"v,xOA,X",	4 },
+{ "stvd",	0xd0000002,	0xfc080002,	"v,xOA,X",	4 },
+
+{ "trr",	0x2c000000,	0xfc0f0000,	"r,R",		2 },
+{ "trn",	0x2c040000,	0xfc0f0000,	"r,R",		2 },
+{ "trnd",	0x2c0c0000,	0xfc0f0000,	"r,R",		2 },
+{ "trabs",	0x2c010000,	0xfc0f0000,	"r,R",		2 },
+{ "trabsd",	0x2c090000,	0xfc0f0000,	"r,R",		2 },
+{ "trc",	0x2c030000,	0xfc0f0000,	"r,R",		2 },
+{ "xcr",	0x28040000,	0xfc0f0000,	"r,R",		2 },
+{ "cxcr",	0x2c060000,	0xfc0f0000,	"r,R",		2 },
+{ "cxcrd",	0x2c0e0000,	0xfc0f0000,	"r,R",		2 },
+{ "tbrr",	0x2c020000,	0xfc0f0000,	"r,B",		2 },
+{ "trbr",	0x28030000,	0xfc0f0000,	"b,R",		2 },
+{ "xcbr",	0x28020000,	0xfc0f0000,	"b,B",		2 },
+{ "tbrbr",	0x28010000,	0xfc0f0000,	"b,B",		2 },
+
+{ "trvv",	0x28050000,	0xfc0f0000,	"v,V",		2 },
+{ "trvvn",	0x2c050000,	0xfc0f0000,	"v,V",		2 },
+{ "trvvnd",	0x2c0d0000,	0xfc0f0000,	"v,V",		2 },
+{ "trvab",	0x2c070000,	0xfc0f0000,	"v,V",		2 },
+{ "trvabd",	0x2c0f0000,	0xfc0f0000,	"v,V",		2 },
+{ "cmpv",	0x14060000,	0xfc0f0000,	"v,V",		2 },
+{ "expv",	0x14070000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvlt",	0x10030000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvle",	0x10040000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvgt",	0x14030000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvge",	0x14040000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvveq",	0x10050000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvne",	0x10050000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvrlt",	0x100d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrle",	0x100e0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrgt",	0x140d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrge",	0x140e0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvreq",	0x100f0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrne",	0x140f0000,	0xfc0f0000,	"v,R",		2 },
+{ "trvr",	0x140b0000,	0xfc0f0000,	"r,V",		2 },
+{ "trrv",	0x140c0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "bu",		0x40000000,	0xff880000,	"xOA,X",	4 },
+{ "bns",	0x70080000,	0xff880000,	"xOA,X",	4 },
+{ "bnco",	0x70880000,	0xff880000,	"xOA,X",	4 },
+{ "bge",	0x71080000,	0xff880000,	"xOA,X",	4 },
+{ "bne",	0x71880000,	0xff880000,	"xOA,X",	4 },
+{ "bunge",	0x72080000,	0xff880000,	"xOA,X",	4 },
+{ "bunle",	0x72880000,	0xff880000,	"xOA,X",	4 },
+{ "bgt",	0x73080000,	0xff880000,	"xOA,X",	4 },
+{ "bnany",	0x73880000,	0xff880000,	"xOA,X",	4 },
+{ "bs"	,	0x70000000,	0xff880000,	"xOA,X",	4 },
+{ "bco",	0x70800000,	0xff880000,	"xOA,X",	4 },
+{ "blt",	0x71000000,	0xff880000,	"xOA,X",	4 },
+{ "beq",	0x71800000,	0xff880000,	"xOA,X",	4 },
+{ "buge",	0x72000000,	0xff880000,	"xOA,X",	4 },
+{ "bult",	0x72800000,	0xff880000,	"xOA,X",	4 },
+{ "ble",	0x73000000,	0xff880000,	"xOA,X",	4 },
+{ "bany",	0x73800000,	0xff880000,	"xOA,X",	4 },
+{ "brlnk",	0x44000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bib",	0x48000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bih",	0x48080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "biw",	0x4c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bid",	0x4c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivb",	0x60000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivh",	0x60080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivw",	0x64000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivd",	0x64080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsb",	0x68000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsh",	0x68080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsw",	0x6c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsd",	0x6c080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "camb",	0x80080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camh",	0x80000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "camw",	0x80000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camd",	0x80000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "car",	0x10000000,	0xfc0f0000,	"r,R",		2 },
+{ "card",	0x14000000,	0xfc0f0000,	"r,R",		2 },
+{ "ci",		0xf8050000,	0xfc7f0000,	"r,I",		4 },
+{ "chkbnd",	0x5c080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "cavv",	0x10010000,	0xfc0f0000,	"v,V",		2 },
+{ "cavr",	0x10020000,	0xfc0f0000,	"v,R",		2 },
+{ "cavvd",	0x10090000,	0xfc0f0000,	"v,V",		2 },
+{ "cavrd",	0x100b0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "anmb",	0x84080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmh",	0x84000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "anmw",	0x84000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmd",	0x84000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "anr",	0x04000000,	0xfc0f0000,	"r,R",		2 },
+{ "ani",	0xf8080000,	0xfc7f0000,	"r,I",		4 },
+{ "ormb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "ormw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "orr",	0x08000000,	0xfc0f0000,	"r,R",		2 },
+{ "oi",		0xf8090000,	0xfc7f0000,	"r,I",		4 },
+{ "eomb",	0x8c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomh",	0x8c000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "eomw",	0x8c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomd",	0x8c000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "eor",	0x0c000000,	0xfc0f0000,	"r,R",		2 },
+{ "eoi",	0xf80a0000,	0xfc7f0000,	"r,I",		4 },
+
+{ "anvv",	0x04010000,	0xfc0f0000,	"v,V",		2 },
+{ "anvr",	0x04020000,	0xfc0f0000,	"v,R",		2 },
+{ "orvv",	0x08010000,	0xfc0f0000,	"v,V",		2 },
+{ "orvr",	0x08020000,	0xfc0f0000,	"v,R",		2 },
+{ "eovv",	0x0c010000,	0xfc0f0000,	"v,V",		2 },
+{ "eovr",	0x0c020000,	0xfc0f0000,	"v,R",		2 },
+
+{ "sacz",	0x100c0000,	0xfc0f0000,	"r,R",		2 },
+{ "sla",	0x1c400000,	0xfc600000,	"r,S",		2 },
+{ "sll",	0x1c600000,	0xfc600000,	"r,S",		2 },
+{ "slc",	0x24400000,	0xfc600000,	"r,S",		2 },
+{ "slad",	0x20400000,	0xfc600000,	"r,S",		2 },
+{ "slld",	0x20600000,	0xfc600000,	"r,S",		2 },
+{ "sra",	0x1c000000,	0xfc600000,	"r,S",		2 },
+{ "srl",	0x1c200000,	0xfc600000,	"r,S",		2 },
+{ "src",	0x24000000,	0xfc600000,	"r,S",		2 },
+{ "srad",	0x20000000,	0xfc600000,	"r,S",		2 },
+{ "srld",	0x20200000,	0xfc600000,	"r,S",		2 },
+{ "sda",	0x3c030000,	0xfc0f0000,	"r,R",		2 },
+{ "sdl",	0x3c020000,	0xfc0f0000,	"r,R",		2 },
+{ "sdc",	0x3c010000,	0xfc0f0000,	"r,R",		2 },
+{ "sdad",	0x3c0b0000,	0xfc0f0000,	"r,R",		2 },
+{ "sdld",	0x3c0a0000,	0xfc0f0000,	"r,R",		2 },
+
+{ "svda",	0x3c070000,	0xfc0f0000,	"v,R",		2 },
+{ "svdl",	0x3c060000,	0xfc0f0000,	"v,R",		2 },
+{ "svdc",	0x3c050000,	0xfc0f0000,	"v,R",		2 },
+{ "svdad",	0x3c0e0000,	0xfc0f0000,	"v,R",		2 },
+{ "svdld",	0x3c0d0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "sbm",	0xac080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zbm",	0xac000000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tbm",	0xa8080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "incmb",	0xa0000000,	0xfc080000,	"xOA,X",	4 },
+{ "incmh",	0xa0080000,	0xfc080000,	"xOA,X",	4 },
+{ "incmw",	0xa4000000,	0xfc080000,	"xOA,X",	4 },
+{ "incmd",	0xa4080000,	0xfc080000,	"xOA,X",	4 },
+{ "sbmd",	0x7c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zbmd",	0x7c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "tbmd",	0x78080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "ssm",	0x9c080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zsm",	0x9c000000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tsm",	0x98080000,	0xfc080000,	"f,xOA,X",	4 },
+
+{ "admb",	0xc8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admh",	0xc8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "admw",	0xc8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admd",	0xc8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adr",	0x38000000,	0xfc0f0000,	"r,R",		2 },
+{ "armb",	0xe8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armh",	0xe8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "armw",	0xe8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armd",	0xe8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adi",	0xf8010000,	0xfc0f0000,	"r,I",		4 },
+{ "sumb",	0xcc080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumh",	0xcc000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "sumw",	0xcc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumd",	0xcc000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sur",	0x3c000000,	0xfc0f0000,	"r,R",		2 },
+{ "sui",	0xf8020000,	0xfc0f0000,	"r,I",		4 },
+{ "mpmb",	0xc0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpmh",	0xc0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "mpmw",	0xc0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpr",	0x38020000,	0xfc0f0000,	"r,R",		2 },
+{ "mprd",	0x3c0f0000,	0xfc0f0000,	"r,R",		2 },
+{ "mpi",	0xf8030000,	0xfc0f0000,	"r,I",		4 },
+{ "dvmb",	0xc4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvmh",	0xc4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "dvmw",	0xc4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvr",	0x380a0000,	0xfc0f0000,	"r,R",		2 },
+{ "dvi",	0xf8040000,	0xfc0f0000,	"r,I",		4 },
+{ "exs",	0x38080000,	0xfc0f0000,	"r,R",		2 },
+
+{ "advv",	0x30000000,	0xfc0f0000,	"v,V",		2 },
+{ "advvd",	0x30080000,	0xfc0f0000,	"v,V",		2 },
+{ "adrv",	0x34000000,	0xfc0f0000,	"v,R",		2 },
+{ "adrvd",	0x34080000,	0xfc0f0000,	"v,R",		2 },
+{ "suvv",	0x30010000,	0xfc0f0000,	"v,V",		2 },
+{ "suvvd",	0x30090000,	0xfc0f0000,	"v,V",		2 },
+{ "surv",	0x34010000,	0xfc0f0000,	"v,R",		2 },
+{ "survd",	0x34090000,	0xfc0f0000,	"v,R",		2 },
+{ "mpvv",	0x30020000,	0xfc0f0000,	"v,V",		2 },
+{ "mprv",	0x34020000,	0xfc0f0000,	"v,R",		2 },
+
+{ "adfw",	0xe0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adfd",	0xe0080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adrfw",	0x38010000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfd",	0x38090000,	0xfc0f0000,	"r,R",		2 },
+{ "surfw",	0xe0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "surfd",	0xe0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "surfw",	0x38030000,	0xfc0f0000,	"r,R",		2 },
+{ "surfd",	0x380b0000,	0xfc0f0000,	"r,R",		2 },
+{ "mpfw",	0xe4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpfd",	0xe4080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "mprfw",	0x38060000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfd",	0x380e0000,	0xfc0f0000,	"r,R",		2 },
+{ "rfw",	0xe4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "rfd",	0xe4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "rrfw",	0x0c0e0000,	0xfc0f0000,	"r",		2 },
+{ "rrfd",	0x0c0f0000,	0xfc0f0000,	"r",		2 },
+
+{ "advvfw",	0x30040000,	0xfc0f0000,	"v,V",		2 },
+{ "advvfd",	0x300c0000,	0xfc0f0000,	"v,V",		2 },
+{ "adrvfw",	0x34040000,	0xfc0f0000,	"v,R",		2 },
+{ "adrvfd",	0x340c0000,	0xfc0f0000,	"v,R",		2 },
+{ "suvvfw",	0x30050000,	0xfc0f0000,	"v,V",		2 },
+{ "suvvfd",	0x300d0000,	0xfc0f0000,	"v,V",		2 },
+{ "survfw",	0x34050000,	0xfc0f0000,	"v,R",		2 },
+{ "survfd",	0x340d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mpvvfw",	0x30060000,	0xfc0f0000,	"v,V",		2 },
+{ "mpvvfd",	0x300e0000,	0xfc0f0000,	"v,V",		2 },
+{ "mprvfw",	0x34060000,	0xfc0f0000,	"v,R",		2 },
+{ "mprvfd",	0x340e0000,	0xfc0f0000,	"v,R",		2 },
+{ "rvfw",	0x30070000,	0xfc0f0000,	"v",		2 },
+{ "rvfd",	0x300f0000,	0xfc0f0000,	"v",		2 },
+
+{ "fltw",	0x38070000,	0xfc0f0000,	"r,R",		2 },
+{ "fltd",	0x380f0000,	0xfc0f0000,	"r,R",		2 },
+{ "fixw",	0x38050000,	0xfc0f0000,	"r,R",		2 },
+{ "fixd",	0x380d0000,	0xfc0f0000,	"r,R",		2 },
+{ "cfpds",	0x3c090000,	0xfc0f0000,	"r,R",		2 },
+
+{ "fltvw",	0x080d0000,	0xfc0f0000,	"v,V",		2 },
+{ "fltvd",	0x080f0000,	0xfc0f0000,	"v,V",		2 },
+{ "fixvw",	0x080c0000,	0xfc0f0000,	"v,V",		2 },
+{ "fixvd",	0x080e0000,	0xfc0f0000,	"v,V",		2 },
+{ "cfpvds",	0x0c0d0000,	0xfc0f0000,	"v,V",		2 },
+
+{ "orvrn",	0x000a0000,	0xfc0f0000,	"r,V",		2 },
+{ "andvrn",	0x00080000,	0xfc0f0000,	"r,V",		2 },
+{ "frsteq",	0x04090000,	0xfc0f0000,	"r,V",		2 },
+{ "sigma",	0x0c080000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmad",	0x0c0a0000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmf",	0x08080000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmfd",	0x080a0000,	0xfc0f0000,	"r,V",		2 },
+{ "prodf",	0x04080000,	0xfc0f0000,	"r,V",		2 },
+{ "prodfd",	0x040a0000,	0xfc0f0000,	"r,V",		2 },
+{ "maxv",	0x10080000,	0xfc0f0000,	"r,V",		2 },
+{ "maxvd",	0x100a0000,	0xfc0f0000,	"r,V",		2 },
+{ "minv",	0x14080000,	0xfc0f0000,	"r,V",		2 },
+{ "minvd",	0x140a0000,	0xfc0f0000,	"r,V",		2 },
+
+{ "lpsd",	0xf0000000,	0xfc080000,	"xOA,X",	4 },
+{ "ldc",	0xf0080000,	0xfc080000,	"xOA,X",	4 },
+{ "spm",	0x040c0000,	0xfc0f0000,	"r",		2 },
+{ "rpm",	0x040d0000,	0xfc0f0000,	"r",		2 },
+{ "tritr",	0x00070000,	0xfc0f0000,	"r",		2 },
+{ "trrit",	0x00060000,	0xfc0f0000,	"r",		2 },
+{ "rpswt",	0x04080000,	0xfc0f0000,	"r",		2 },
+{ "exr",	0xf8070000,	0xfc0f0000,	"",		4 },
+{ "halt",	0x00000000,	0xfc0f0000,	"",		2 },
+{ "wait",	0x00010000,	0xfc0f0000,	"",		2 },
+{ "nop",	0x00020000,	0xfc0f0000,	"",		2 },
+{ "eiae",	0x00030000,	0xfc0f0000,	"",		2 },
+{ "efae",	0x000d0000,	0xfc0f0000,	"",		2 },
+{ "diae",	0x000e0000,	0xfc0f0000,	"",		2 },
+{ "dfae",	0x000f0000,	0xfc0f0000,	"",		2 },
+{ "spvc",	0xf8060000,	0xfc0f0000,	"r,T,N",	4 },
+{ "rdsts",	0x00090000,	0xfc0f0000,	"r",		2 },
+{ "setcpu",	0x000c0000,	0xfc0f0000,	"r",		2 },
+{ "cmc",	0x000b0000,	0xfc0f0000,	"r",		2 },
+{ "trrcu",	0x00040000,	0xfc0f0000,	"r",		2 },
+{ "attnio",	0x00050000,	0xfc0f0000,	"",		2 },
+{ "fudit",	0x28080000,	0xfc0f0000,	"",		2 },
+{ "break",	0x28090000,	0xfc0f0000,	"",		2 },
+{ "frzss",	0x280a0000,	0xfc0f0000,	"",		2 },
+{ "ripi",	0x04040000,	0xfc0f0000,	"r,R",		2 },
+{ "xcp",	0x04050000,	0xfc0f0000,	"r",		2 },
+{ "block",	0x04060000,	0xfc0f0000,	"",		2 },
+{ "unblock",	0x04070000,	0xfc0f0000,	"",		2 },
+{ "trsc",	0x08060000,	0xfc0f0000,	"r,R",		2 },
+{ "tscr",	0x08070000,	0xfc0f0000,	"r,R",		2 },
+{ "fq",		0x04080000,	0xfc0f0000,	"r",		2 },
+{ "flupte",	0x2c080000,	0xfc0f0000,	"r",		2 },
+{ "rviu",	0x040f0000,	0xfc0f0000,	"",		2 },
+{ "ldel",	0x280c0000,	0xfc0f0000,	"r,R",		2 },
+{ "ldu",	0x280d0000,	0xfc0f0000,	"r,R",		2 },
+{ "stdecc",	0x280b0000,	0xfc0f0000,	"r,R",		2 },
+{ "trpc",	0x08040000,	0xfc0f0000,	"r",		2 },
+{ "tpcr",	0x08050000,	0xfc0f0000,	"r",		2 },
+{ "ghalt",	0x0c050000,	0xfc0f0000,	"r",		2 },
+{ "grun",	0x0c040000,	0xfc0f0000,	"",		2 },
+{ "tmpr",	0x2c0a0000,	0xfc0f0000,	"r,R",		2 },
+{ "trmp",	0x2c0b0000,	0xfc0f0000,	"r,R",		2 },
+
+{ "trrve",	0x28060000,	0xfc0f0000,	"r",		2 },
+{ "trver",	0x28070000,	0xfc0f0000,	"r",		2 },
+{ "trvlr",	0x280f0000,	0xfc0f0000,	"r",		2 },
+
+{ "linkfl",	0x18000000,	0xfc0f0000,	"r,R",		2 },
+{ "linkbl",	0x18020000,	0xfc0f0000,	"r,R",		2 },
+{ "linkfp",	0x18010000,	0xfc0f0000,	"r,R",		2 },
+{ "linkbp",	0x18030000,	0xfc0f0000,	"r,R",		2 },
+{ "linkpl",	0x18040000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinkl",	0x18080000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinkp",	0x18090000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinktl",	0x180a0000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinktp",	0x180b0000,	0xfc0f0000,	"r,R",		2 },
+};
+
+int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
+
+struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
+		 		sizeof(gld_opcodes[0]);
diff --git a/contrib/binutils/include/opcode/pn.h b/contrib/binutils/include/opcode/pn.h
new file mode 100644
index 000000000000..0f59a2a53ce9
--- /dev/null
+++ b/contrib/binutils/include/opcode/pn.h
@@ -0,0 +1,282 @@
+/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+struct gld_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long mask;
+  char *args;
+  int length;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and at most four.  The length of the
+   instruction is based on the opcode.
+
+   The mask component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing characters
+   that are used to format the arguments to the instruction. */
+
+/* Kinds of operands:
+   r  Register in first field
+   R  Register in second field
+   b  Base register in first field
+   B  Base register in second field
+   v  Vector register in first field
+   V  Vector register in first field
+   A  Optional address register (base register)
+   X  Optional index register
+   I  Immediate data (16bits signed)
+   O  Offset field (16bits signed)
+   h  Offset field (15bits signed)
+   d  Offset field (14bits signed)
+   S  Shift count field
+
+   any other characters are printed as is...
+*/
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+struct gld_opcode gld_opcodes[] =
+{
+{ "abm",	0xa0080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "abr",	0x18080000,	0xfc0c0000,	"r,f",		2 },
+{ "aci",	0xfc770000,	0xfc7f8000,	"r,I",		4 },
+{ "adfd",	0xe0080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adfw",	0xe0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adi",	0xc8010000,	0xfc7f0000,	"r,I",		4 },
+{ "admb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "admh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "admw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adr",	0x38000000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfd",	0x38090000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfw",	0x38010000,	0xfc0f0000,	"r,R",		2 },
+{ "adrm",	0x38080000,	0xfc0f0000,	"r,R",		2 },
+{ "ai", 	0xfc030000,	0xfc07ffff,	"I",		4 },
+{ "anmb",	0x84080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmd",	0x84000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "anmh",	0x84000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "anmw",	0x84000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anr",	0x04000000,	0xfc0f0000,	"r,R",		2 },
+{ "armb",	0xe8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armd",	0xe8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "armh",	0xe8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "armw",	0xe8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bcf",	0xf0000000,	0xfc080000,	"I,xOA,X",	4 },
+{ "bct",	0xec000000,	0xfc080000,	"I,xOA,X",	4 },
+{ "bei",	0x00060000,	0xffff0000,	"",		2 },
+{ "bft",	0xf0000000,	0xff880000,	"xOA,X",	4 },
+{ "bib",	0xf4000000,	0xfc780000,	"r,xOA",	4 },
+{ "bid",	0xf4600000,	0xfc780000,	"r,xOA",	4 },
+{ "bih",	0xf4200000,	0xfc780000,	"r,xOA",	4 },
+{ "biw",	0xf4400000,	0xfc780000,	"r,xOA",	4 },
+{ "bl", 	0xf8800000,	0xff880000,	"xOA,X",	4 },
+{ "bsub",	0x5c080000,	0xff8f0000,	"",		2 },
+{ "bsubm",	0x28080000,	0xfc080000,	"",		4 },
+{ "bu", 	0xec000000,	0xff880000,	"xOA,X",	4 },
+{ "call",	0x28080000,	0xfc0f0000,	"",		2 },
+{ "callm",	0x5c080000,	0xff880000,	"",		4 },
+{ "camb",	0x90080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camd",	0x90000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "camh",	0x90000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "camw",	0x90000000,	0xfc080000,	"r.xOA,X",	4 },
+{ "car",	0x10000000,	0xfc0f0000,	"r,R",		2 },
+{ "cd", 	0xfc060000,	0xfc070000,	"r,f",		4 },
+{ "cea",	0x000f0000,	0xffff0000,	"",		2 },
+{ "ci", 	0xc8050000,	0xfc7f0000,	"r,I",		4 },
+{ "cmc",	0x040a0000,	0xfc7f0000,	"r",		2 },
+{ "cmmb",	0x94080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "cmmd",	0x94000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "cmmh",	0x94000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "cmmw",	0x94000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "cmr",	0x14000000,	0xfc0f0000,	"r,R",		2 },
+{ "daci",	0xfc7f0000,	0xfc7f8000,	"r,I",		4 },
+{ "dae",	0x000e0000,	0xffff0000,	"",		2 },
+{ "dai",	0xfc040000,	0xfc07ffff,	"I",		4 },
+{ "dci",	0xfc6f0000,	0xfc7f8000,	"r,I",		4 },
+{ "di", 	0xfc010000,	0xfc07ffff,	"I",		4 },
+{ "dvfd",	0xe4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "dvfw",	0xe4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvi",	0xc8040000,	0xfc7f0000,	"r,I",		4 },
+{ "dvmb",	0xc4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvmh",	0xc4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "dvmw",	0xc4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvr",	0x380a0000,	0xfc0f0000,	"r,R",		2 },
+{ "dvrfd",	0x380c0000,	0xfc0f0000,	"r,R",		4 },
+{ "dvrfw",	0x38040000,	0xfc0f0000,	"r,xOA,X",	4 },
+{ "eae",	0x00080000,	0xffff0000,	"",		2 },
+{ "eci",	0xfc670000,	0xfc7f8080,	"r,I",		4 },
+{ "ecwcs",	0xfc4f0000,	0xfc7f8000,	"",		4 },
+{ "ei", 	0xfc000000,	0xfc07ffff,	"I",		4 },
+{ "eomb",	0x8c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomd",	0x8c000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "eomh",	0x8c000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "eomw",	0x8c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eor",	0x0c000000,	0xfc0f0000,	"r,R",		2 },
+{ "eorm",	0x0c080000,	0xfc0f0000,	"r,R",		2 },
+{ "es", 	0x00040000,	0xfc7f0000,	"r",		2 },
+{ "exm",	0xa8000000,	0xff880000,	"xOA,X",	4 },
+{ "exr",	0xc8070000,	0xfc7f0000,	"r",		2 },
+{ "exrr",	0xc8070002,	0xfc7f0002,	"r",		2 },
+{ "fixd",	0x380d0000,	0xfc0f0000,	"r,R",		2 },
+{ "fixw",	0x38050000,	0xfc0f0000,	"r,R",		2 },
+{ "fltd",	0x380f0000,	0xfc0f0000,	"r,R",		2 },
+{ "fltw",	0x38070000,	0xfc0f0000,	"r,R",		2 },
+{ "grio",	0xfc3f0000,	0xfc7f8000,	"r,I",		4 },
+{ "halt",	0x00000000,	0xffff0000,	"",		2 },
+{ "hio",	0xfc370000,	0xfc7f8000,	"r,I",		4 },
+{ "jwcs",	0xfa080000,	0xff880000,	"xOA,X",	4 },
+{ "la", 	0x50000000,	0xfc000000,	"r,xOA,X",	4 },
+{ "labr",	0x58080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lb", 	0xac080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lcs", 	0x00030000,	0xfc7f0000,	"r",		2 },
+{ "ld", 	0xac000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lear", 	0x80000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lf", 	0xcc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lfbr", 	0xcc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lh", 	0xac000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "li", 	0xc8000000,	0xfc7f0000,	"r,I",		4 },
+{ "lmap",	0x2c070000,	0xfc7f0000,	"r",		2 },
+{ "lmb",	0xb0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lmd",	0xb0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lmh",	0xb0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lmw",	0xb0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnb",	0xb4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnd",	0xb4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lnh",	0xb4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lnw",	0xb4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lpsd",	0xf9800000,	0xff880000,	"r,xOA,X",	4 },
+{ "lpsdcm",	0xfa800000,	0xff880000,	"r,xOA,X",	4 },
+{ "lw", 	0xac000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwbr", 	0x5c000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "mpfd",	0xe4080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "mpfw",	0xe4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpi",	0xc8030000,	0xfc7f0000,	"r,I",		4 },
+{ "mpmb",	0xc0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpmh",	0xc0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "mpmw",	0xc0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpr",	0x38020000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfd",	0x380e0000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfw",	0x38060000,	0xfc0f0000,	"r,R",		2 },
+{ "nop",	0x00020000,	0xffff0000,	"",		2 },
+{ "ormb",	0x88080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormd",	0x88000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "ormh",	0x88000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "ormw",	0x88000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "orr",	0x08000000,	0xfc0f0000,	"r,R",		2 },
+{ "orrm",	0x08080000,	0xfc0f0000,	"r,R",		2 },
+{ "rdsts",	0x00090000,	0xfc7f0000,	"r",		2 },
+{ "return",	0x280e0000,	0xfc7f0000,	"",		2 },
+{ "ri", 	0xfc020000,	0xfc07ffff,	"I",		4 },
+{ "rnd",	0x00050000,	0xfc7f0000,	"r",		2 },
+{ "rpswt",	0x040b0000,	0xfc7f0000,	"r",		2 },
+{ "rschnl",	0xfc2f0000,	0xfc7f8000,	"r,I",		4 },
+{ "rsctl",	0xfc470000,	0xfc7f8000,	"r,I",		4 },
+{ "rwcs",	0x000b0000,	0xfc0f0000,	"r,R",		2 },
+{ "sacz",	0x10080000,	0xfc0f0000,	"r,R",		2 },
+{ "sbm",	0x98080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "sbr",	0x18000000,	0xfc0c0000,	"r,f",		4 },
+{ "sea",	0x000d0000,	0xffff0000,	"",		2 },
+{ "setcpu",	0x2c090000,	0xfc7f0000,	"r",		2 },
+{ "sio",	0xfc170000,	0xfc7f8000,	"r,I",		4 },
+{ "sipu",	0x000a0000,	0xffff0000,	"",		2 },
+{ "sla",	0x1c400000,	0xfc600000,	"r,S",		2 },
+{ "slad",	0x20400000,	0xfc600000,	"r,S",		2 },
+{ "slc",	0x24400000,	0xfc600000,	"r,S",		2 },
+{ "sll",	0x1c600000,	0xfc600000,	"r,S",		2 },
+{ "slld",	0x20600000,	0xfc600000,	"r,S",		2 },
+{ "smc",	0x04070000,	0xfc070000,	"",		2 },
+{ "sra",	0x1c000000,	0xfc600000,	"r,S",		2 },
+{ "srad",	0x20000000,	0xfc600000,	"r,S",		2 },
+{ "src",	0x24000000,	0xfc600000,	"r,S",		2 },
+{ "srl",	0x1c200000,	0xfc600000,	"r,S",		2 },
+{ "srld",	0x20200000,	0xfc600000,	"r,S",		2 },
+{ "stb",	0xd4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "std",	0xd4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stf",	0xdc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stfbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "sth",	0xd4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stmb",	0xd8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stmd",	0xd8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stmh",	0xd8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stmw",	0xd8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stpio",	0xfc270000,	0xfc7f8000,	"r,I",		4 },
+{ "stw",	0xd4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stwbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "suabr",	0x58000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "sufd",	0xe0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sufw",	0xe0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sui",	0xc8020000,	0xfc7f0000,	"r,I",		4 },
+{ "sumb",	0xbc080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumd",	0xbc000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sumh",	0xbc000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "sumw",	0xbc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sur",	0x3c000000,	0xfc0f0000,	"r,R",		2 },
+{ "surfd",	0x380b0000,	0xfc0f0000,	"r,xOA,X",	4 },
+{ "surfw",	0x38030000,	0xfc0f0000,	"r,R",		2 },
+{ "surm",	0x3c080000,	0xfc0f0000,	"r,R",		2 },
+{ "svc",	0xc8060000,	0xffff0000,	"",		4 },
+{ "tbm",	0xa4080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tbr",	0x180c0000,	0xfc0c0000,	"r,f",		2 },
+{ "tbrr",	0x2c020000,	0xfc0f0000,	"r,B",		2 },
+{ "tccr",	0x28040000,	0xfc7f0000,	"",		2 },
+{ "td", 	0xfc050000,	0xfc070000,	"r,f",		4 },
+{ "tio",	0xfc1f0000,	0xfc7f8000,	"r,I",		4 },
+{ "tmapr",	0x2c0a0000,	0xfc0f0000,	"r,R",		2 },
+{ "tpcbr",	0x280c0000,	0xfc7f0000,	"r",		2 },
+{ "trbr",	0x2c010000,	0xfc0f0000,	"b,R",		2 },
+{ "trc",	0x2c030000,	0xfc0f0000,	"r,R",		2 },
+{ "trcc",	0x28050000,	0xfc7f0000,	"",		2 },
+{ "trcm",	0x2c0b0000,	0xfc0f0000,	"r,R",		2 },
+{ "trn",	0x2c040000,	0xfc0f0000,	"r,R",		2 },
+{ "trnm",	0x2c0c0000,	0xfc0f0000,	"r,R",		2 },
+{ "trr",	0x2c000000,	0xfc0f0000,	"r,R",		2 },
+{ "trrm",	0x2c080000,	0xfc0f0000,	"r,R",		2 },
+{ "trsc",	0x2c0e0000,	0xfc0f0000,	"r,R",		2 },
+{ "trsw",	0x28000000,	0xfc7f0000,	"r",		2 },
+{ "tscr",	0x2c0f0000,	0xfc0f0000,	"r,R",		2 },
+{ "uei",	0x00070000,	0xffff0000,	"",		2 },
+{ "wait",	0x00010000,	0xffff0000,	"",		2 },
+{ "wcwcs",	0xfc5f0000,	0xfc7f8000,	"",		4 },
+{ "wwcs",	0x000c0000,	0xfc0f0000,	"r,R",		2 },
+{ "xcbr",	0x28020000,	0xfc0f0000,	"b,B",		2 },
+{ "xcr",	0x2c050000,	0xfc0f0000,	"r,R",		2 },
+{ "xcrm",	0x2c0d0000,	0xfc0f0000,	"r,R",		2 },
+{ "zbm",	0x9c080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zbr",	0x18040000,	0xfc0c0000,	"r,f",		2 },
+{ "zmb",	0xf8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmd",	0xf8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "zmh",	0xf8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "zmw",	0xf8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zr", 	0x0c000000,	0xfc0f0000,	"r",		2 },
+};
+
+int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
+
+struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
+		sizeof(gld_opcodes[0]);