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| author | Andriy Gapon <avg@FreeBSD.org> | 2011-05-06 13:51:54 +0000 |
|---|---|---|
| committer | Andriy Gapon <avg@FreeBSD.org> | 2011-05-06 13:51:54 +0000 |
| commit | fdf30d59a69e04ce448694c1249c514685440f07 (patch) | |
| tree | 91ee463830e2079554023ddf7655e38485c5d532 | |
| parent | f9a94737022976d908e983a465dbe913b758d0f0 (diff) | |
| download | src-fdf30d59a69e04ce448694c1249c514685440f07.tar.gz src-fdf30d59a69e04ce448694c1249c514685440f07.zip | |
prepare code that does topology detection for amd cpus for bulldozer
This also introduces a new detection path for family 10h and newer
pre-bulldozer cpus, pre-10h hardware should not be affected.
Tested by: Gary Jennejohn <gljennjohn@googlemail.com>
(with pre-10h hardware)
MFC after: 2 weeks
Notes
Notes:
svn path=/head/; revision=221527
| -rw-r--r-- | sys/amd64/amd64/mp_machdep.c | 27 | ||||
| -rw-r--r-- | sys/amd64/include/specialreg.h | 2 | ||||
| -rw-r--r-- | sys/i386/i386/mp_machdep.c | 27 | ||||
| -rw-r--r-- | sys/i386/include/specialreg.h | 2 |
4 files changed, 54 insertions, 4 deletions
diff --git a/sys/amd64/amd64/mp_machdep.c b/sys/amd64/amd64/mp_machdep.c index 8e8dc67bdc1c..5c900344518b 100644 --- a/sys/amd64/amd64/mp_machdep.c +++ b/sys/amd64/amd64/mp_machdep.c @@ -176,11 +176,34 @@ mem_range_AP_init(void) static void topo_probe_amd(void) { + int core_id_bits; + int id; /* AMD processors do not support HTT. */ - cpu_cores = (amd_feature2 & AMDID2_CMP) != 0 ? - (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; cpu_logical = 1; + + if ((amd_feature2 & AMDID2_CMP) == 0) { + cpu_cores = 1; + return; + } + + core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> + AMDID_COREID_SIZE_SHIFT; + if (core_id_bits == 0) { + cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; + return; + } + + /* Fam 10h and newer should get here. */ + for (id = 0; id <= MAX_APIC_ID; id++) { + /* Check logical CPU availability. */ + if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) + continue; + /* Check if logical CPU has the same package ID. */ + if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) + continue; + cpu_cores++; + } } /* diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 9428dd906125..ac5206358b5e 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -228,6 +228,8 @@ * AMD extended function 8000_0008h ecx info */ #define AMDID_CMP_CORES 0x000000ff +#define AMDID_COREID_SIZE 0x0000f000 +#define AMDID_COREID_SIZE_SHIFT 12 /* * CPUID manufacturers identifiers diff --git a/sys/i386/i386/mp_machdep.c b/sys/i386/i386/mp_machdep.c index 871ccb49f5f0..a4db4016f8e9 100644 --- a/sys/i386/i386/mp_machdep.c +++ b/sys/i386/i386/mp_machdep.c @@ -224,11 +224,34 @@ mem_range_AP_init(void) static void topo_probe_amd(void) { + int core_id_bits; + int id; /* AMD processors do not support HTT. */ - cpu_cores = (amd_feature2 & AMDID2_CMP) != 0 ? - (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; cpu_logical = 1; + + if ((amd_feature2 & AMDID2_CMP) == 0) { + cpu_cores = 1; + return; + } + + core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> + AMDID_COREID_SIZE_SHIFT; + if (core_id_bits == 0) { + cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; + return; + } + + /* Fam 10h and newer should get here. */ + for (id = 0; id <= MAX_APIC_ID; id++) { + /* Check logical CPU availability. */ + if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) + continue; + /* Check if logical CPU has the same package ID. */ + if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) + continue; + cpu_cores++; + } } /* diff --git a/sys/i386/include/specialreg.h b/sys/i386/include/specialreg.h index cfb205f17ff0..adccaf4483f9 100644 --- a/sys/i386/include/specialreg.h +++ b/sys/i386/include/specialreg.h @@ -227,6 +227,8 @@ * AMD extended function 8000_0008h ecx info */ #define AMDID_CMP_CORES 0x000000ff +#define AMDID_COREID_SIZE 0x0000f000 +#define AMDID_COREID_SIZE_SHIFT 12 /* * CPUID manufacturers identifiers |