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author | Hans Petter Selasky <hselasky@FreeBSD.org> | 2019-10-02 09:56:27 +0000 |
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committer | Hans Petter Selasky <hselasky@FreeBSD.org> | 2019-10-02 09:56:27 +0000 |
commit | 8ae1c36f8b5afddd4a5ab04d3fe6fa03bfc80174 (patch) | |
tree | df167f2589698b5532667e97bb7d4ae22d420c9a | |
parent | 6b4040d8ff02e6880a0ad0caf38d1f66b0895ab2 (diff) | |
download | src-8ae1c36f8b5afddd4a5ab04d3fe6fa03bfc80174.tar.gz src-8ae1c36f8b5afddd4a5ab04d3fe6fa03bfc80174.zip |
Sort the ports registers definitions numerically in mlx5core.
Submitted by: kib@
MFC after: 3 days
Sponsored by: Mellanox Technologies
Notes
Notes:
svn path=/head/; revision=352977
-rw-r--r-- | sys/dev/mlx5/driver.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/sys/dev/mlx5/driver.h b/sys/dev/mlx5/driver.h index a1a3c7c6391c..bc9b929df9dd 100644 --- a/sys/dev/mlx5/driver.h +++ b/sys/dev/mlx5/driver.h @@ -126,24 +126,24 @@ enum { MLX5_REG_QCAM = 0x4019, MLX5_REG_DCBX_PARAM = 0x4020, MLX5_REG_DCBX_APP = 0x4021, - MLX5_REG_PCAP = 0x5001, MLX5_REG_FPGA_CAP = 0x4022, MLX5_REG_FPGA_CTRL = 0x4023, MLX5_REG_FPGA_ACCESS_REG = 0x4024, MLX5_REG_FPGA_SHELL_CNTR = 0x4025, + MLX5_REG_PCAP = 0x5001, + MLX5_REG_PMLP = 0x5002, MLX5_REG_PMTU = 0x5003, MLX5_REG_PTYS = 0x5004, MLX5_REG_PAOS = 0x5006, MLX5_REG_PFCC = 0x5007, MLX5_REG_PPCNT = 0x5008, - MLX5_REG_PMAOS = 0x5012, MLX5_REG_PUDE = 0x5009, MLX5_REG_PPTB = 0x500B, MLX5_REG_PBMC = 0x500C, + MLX5_REG_PELC = 0x500E, + MLX5_REG_PVLC = 0x500F, MLX5_REG_PMPE = 0x5010, - MLX5_REG_PELC = 0x500e, - MLX5_REG_PVLC = 0x500f, - MLX5_REG_PMLP = 0x5002, + MLX5_REG_PMAOS = 0x5012, MLX5_REG_PCAM = 0x507f, MLX5_REG_NODE_DESC = 0x6001, MLX5_REG_HOST_ENDIANNESS = 0x7004, |