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author | Warner Losh <imp@FreeBSD.org> | 2012-08-11 05:45:19 +0000 |
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committer | Warner Losh <imp@FreeBSD.org> | 2012-08-11 05:45:19 +0000 |
commit | 56c265f2f923b9ae7379e68ff5196b5d639f1bfa (patch) | |
tree | 338892b0584817392a198ad882703d8d288d1183 | |
parent | bcc1a5425ac3bb5fffc0058d0da9395772040626 (diff) | |
download | src-56c265f2f923b9ae7379e68ff5196b5d639f1bfa.tar.gz src-56c265f2f923b9ae7379e68ff5196b5d639f1bfa.zip |
Correct the PLLA setting functions and centralize.
Notes
Notes:
svn path=/head/; revision=239190
-rw-r--r-- | sys/arm/at91/at91_pmc.c | 34 | ||||
-rw-r--r-- | sys/arm/at91/at91_pmcvar.h | 2 | ||||
-rw-r--r-- | sys/arm/at91/at91sam9g20.c | 28 | ||||
-rw-r--r-- | sys/arm/at91/at91sam9g45.c | 19 | ||||
-rw-r--r-- | sys/arm/at91/at91sam9x5.c | 28 |
5 files changed, 41 insertions, 70 deletions
diff --git a/sys/arm/at91/at91_pmc.c b/sys/arm/at91/at91_pmc.c index c8002faeceb2..43a7b9c3f6fc 100644 --- a/sys/arm/at91/at91_pmc.c +++ b/sys/arm/at91/at91_pmc.c @@ -187,6 +187,40 @@ WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val) bus_write_4(sc->mem_res, off, val); } +/* + * The following is unused currently since we don't ever set the PLLA + * frequency of the device. If we did, we'd have to also pay attention + * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower + * than ~600MHz, which the PMC code doesn't do right now. + */ +uint32_t +at91_pmc_800mhz_plla_outb(int freq) +{ + uint32_t outa; + + /* + * Set OUTA, per the data sheet. See Table 46-16 titled + * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc, + * Table 46-17 in the SAM9G20 doc, or Table 46-16 in the SAM9G45 doc. + * Note: the frequencies overlap by 5MHz, so we add 3 here to + * center shoot the transition. + */ + + freq /= 1000000; /* MHz */ + if (freq >= 800) + freq = 800; + freq += 3; /* Allow for overlap. */ + outa = 3 - ((freq / 50) & 3); /* 750 / 50 = 7, see table */ + return (1 << 29)| (outa << 14); +} + +uint32_t +at91_pmc_800mhz_pllb_outb(int freq) +{ + + return (0); +} + void at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on) { diff --git a/sys/arm/at91/at91_pmcvar.h b/sys/arm/at91/at91_pmcvar.h index 1593a85e74e5..700eba18706e 100644 --- a/sys/arm/at91/at91_pmcvar.h +++ b/sys/arm/at91/at91_pmcvar.h @@ -62,4 +62,6 @@ void at91_pmc_clock_deref(struct at91_pmc_clock *); void at91_pmc_clock_enable(struct at91_pmc_clock *); void at91_pmc_clock_disable(struct at91_pmc_clock *); +uint32_t at91_pmc_800mhz_plla_outb(int freq); +uint32_t at91_pmc_800mhz_pllb_outb(int freq); #endif /* ARM_AT91_AT91_PMCVAR_H */ diff --git a/sys/arm/at91/at91sam9g20.c b/sys/arm/at91/at91sam9g20.c index 73876b0542a9..4d9907cdd69f 100644 --- a/sys/arm/at91/at91sam9g20.c +++ b/sys/arm/at91/at91sam9g20.c @@ -122,30 +122,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static uint32_t -at91_pll_outa(int freq) -{ - - switch (freq / 10000000) { - case 747 ... 801: return ((1 << 29) | (0 << 14)); - case 697 ... 746: return ((1 << 29) | (1 << 14)); - case 647 ... 696: return ((1 << 29) | (2 << 14)); - case 597 ... 646: return ((1 << 29) | (3 << 14)); - case 547 ... 596: return ((1 << 29) | (1 << 14)); - case 497 ... 546: return ((1 << 29) | (2 << 14)); - case 447 ... 496: return ((1 << 29) | (3 << 14)); - case 397 ... 446: return ((1 << 29) | (4 << 14)); - default: return (1 << 29); - } -} - -static uint32_t -at91_pll_outb(int freq) -{ - - return (0); -} - static void at91_clock_init(void) { @@ -171,7 +147,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK; clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT; clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK; - clk->set_outb = at91_pll_outa; + clk->set_outb = at91_pmc_800mhz_plla_outb; at91_pmc_clock_deref(clk); clk = at91_pmc_clock_ref("pllb"); @@ -183,7 +159,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK; clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT; clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK; - clk->set_outb = at91_pll_outb; + clk->set_outb = at91_pmc_800mhz_pllb_outb; at91_pmc_clock_deref(clk); } diff --git a/sys/arm/at91/at91sam9g45.c b/sys/arm/at91/at91sam9g45.c index 638c3d9ba687..dedc7ceba2ea 100644 --- a/sys/arm/at91/at91sam9g45.c +++ b/sys/arm/at91/at91sam9g45.c @@ -125,23 +125,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static uint32_t -at91_pll_outa(int freq) -{ - - switch (freq / 10000000) { - case 747 ... 801: return ((1 << 29) | (0 << 14)); - case 697 ... 746: return ((1 << 29) | (1 << 14)); - case 647 ... 696: return ((1 << 29) | (2 << 14)); - case 597 ... 646: return ((1 << 29) | (3 << 14)); - case 547 ... 596: return ((1 << 29) | (4 << 14)); - case 497 ... 546: return ((1 << 29) | (5 << 14)); - case 447 ... 496: return ((1 << 29) | (6 << 14)); - case 397 ... 446: return ((1 << 29) | (7 << 14)); - default: return (1 << 29); - } -} - static void at91_clock_init(void) { @@ -162,7 +145,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK; clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT; clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK; - clk->set_outb = at91_pll_outa; + clk->set_outb = at91_pmc_800mhz_plla_outb; at91_pmc_clock_deref(clk); } diff --git a/sys/arm/at91/at91sam9x5.c b/sys/arm/at91/at91sam9x5.c index 3de9ebdf51b6..dedd1353dd2f 100644 --- a/sys/arm/at91/at91sam9x5.c +++ b/sys/arm/at91/at91sam9x5.c @@ -125,30 +125,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static uint32_t -at91_pll_outa(int freq) -{ - - switch (freq / 10000000) { - case 747 ... 801: return ((1 << 29) | (0 << 14)); - case 697 ... 746: return ((1 << 29) | (1 << 14)); - case 647 ... 696: return ((1 << 29) | (2 << 14)); - case 597 ... 646: return ((1 << 29) | (3 << 14)); - case 547 ... 596: return ((1 << 29) | (1 << 14)); - case 497 ... 546: return ((1 << 29) | (2 << 14)); - case 447 ... 496: return ((1 << 29) | (3 << 14)); - case 397 ... 446: return ((1 << 29) | (4 << 14)); - default: return (1 << 29); - } -} - -static uint32_t -at91_pll_outb(int freq) -{ - - return (0); -} - static void at91_clock_init(void) { @@ -174,7 +150,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9X25_PLL_A_MUL_MASK; clk->pll_div_shift = SAM9X25_PLL_A_DIV_SHIFT; clk->pll_div_mask = SAM9X25_PLL_A_DIV_MASK; - clk->set_outb = at91_pll_outa; + clk->set_outb = at91_pmc_800mhz_plla_outb; at91_pmc_clock_deref(clk); clk = at91_pmc_clock_ref("pllb"); @@ -186,7 +162,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9X25_PLL_B_MUL_MASK; clk->pll_div_shift = SAM9X25_PLL_B_DIV_SHIFT; clk->pll_div_mask = SAM9X25_PLL_B_DIV_MASK; - clk->set_outb = at91_pll_outb; + clk->set_outb = at91_pmc_800mhz_pllb_outb; at91_pmc_clock_deref(clk); } |