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| author | Andrew Turner <andrew@FreeBSD.org> | 2017-05-13 13:03:20 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2017-05-13 13:03:20 +0000 |
| commit | 2438ef7673d5f60c636ea84d37a3a2b503bf0684 (patch) | |
| tree | 7c309c33de5bbae2c0b8d8eca93174677b84a17e | |
| parent | c031b4b01e16c47ef801e99d3b7b9e8e03f4dc31 (diff) | |
| download | src-2438ef7673d5f60c636ea84d37a3a2b503bf0684.tar.gz src-2438ef7673d5f60c636ea84d37a3a2b503bf0684.zip | |
Allocate a cacheline when reading or writing to write through memory. The
hardware will still write to memory, however following reads will be from
the cache.
MFC after: 1 week
Sponsored by: DARPA, AFRL
Notes
Notes:
svn path=/head/; revision=318253
| -rw-r--r-- | sys/arm64/include/armreg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 6a5fde64ef0d..9175bacacd96 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -360,7 +360,7 @@ #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) #define MAIR_DEVICE_nGnRnE 0x00 #define MAIR_NORMAL_NC 0x44 -#define MAIR_NORMAL_WT 0x88 +#define MAIR_NORMAL_WT 0xbb #define MAIR_NORMAL_WB 0xff /* PAR_EL1 - Physical Address Register */ |