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| author | Pyun YongHyeon <yongari@FreeBSD.org> | 2008-12-03 08:56:01 +0000 |
|---|---|---|
| committer | Pyun YongHyeon <yongari@FreeBSD.org> | 2008-12-03 08:56:01 +0000 |
| commit | 19042fb8c79792f52b05738781b09b955a529976 (patch) | |
| tree | 035c7b81259943883e7ff823294394063ebb291b | |
| parent | 1f9cbabcdbd3285c9af7cfeee9aa261c5cfd435e (diff) | |
| download | src-19042fb8c79792f52b05738781b09b955a529976.tar.gz src-19042fb8c79792f52b05738781b09b955a529976.zip | |
Add some PHY magic to enable PHY hibernation and 1000baseT/10baseT
power adjustment. This change is required to guarantee correct
operation on certain switches.
Submitted by: Jie Yang < Jie.Yang <> Atheros com >
Notes
Notes:
svn path=/head/; revision=185576
| -rw-r--r-- | sys/dev/ale/if_ale.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/sys/dev/ale/if_ale.c b/sys/dev/ale/if_ale.c index 0b202eec28f4..afff39c32118 100644 --- a/sys/dev/ale/if_ale.c +++ b/sys/dev/ale/if_ale.c @@ -385,6 +385,39 @@ ale_phy_reset(struct ale_softc *sc) GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); DELAY(1000); + +#define ATPHY_DBG_ADDR 0x1D +#define ATPHY_DBG_DATA 0x1E + + /* Enable hibernation mode. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x0B); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0xBC00); + /* Set Class A/B for all modes. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x00); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0x02EF); + /* Enable 10BT power saving. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x12); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0x4C04); + /* Adjust 1000T power. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x04); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x8BBB); + /* 10BT center tap voltage. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x05); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x2C46); + +#undef ATPHY_DBG_ADDR +#undef ATPHY_DBG_DATA + DELAY(1000); } static int |