From fcc3a0f6302524d6860d64ff472d05c91d117cd3 Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Wed, 8 May 2019 16:06:54 +0000 Subject: Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build. Sponsored by: DARPA, AFRL --- sys/riscv/conf/GENERIC | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'sys/riscv/conf/GENERIC') diff --git a/sys/riscv/conf/GENERIC b/sys/riscv/conf/GENERIC index 33c234b32074..4b692415a194 100644 --- a/sys/riscv/conf/GENERIC +++ b/sys/riscv/conf/GENERIC @@ -102,6 +102,16 @@ device uart # Generic UART driver device uart_lowrisc # lowRISC UART driver device uart_ns8250 # ns8250-type UART driver + +# Ethernet drivers +device miibus # MII bus support +device cgem # Cadence Gigabit Ethernet MAC +device xae # Xilinx AXI Ethernet MAC + +# DMA support +device xdma # DMA interface +device axidma # Xilinx AXI DMA Controller + # Uncomment for memory disk # options MD_ROOT # options MD_ROOT_SIZE=32768 # 32MB ram disk -- cgit v1.2.3