From 1c96bdd14645b8778bd1ec4e0ddcdda18195a99f Mon Sep 17 00:00:00 2001 From: Nathan Whitehorn Date: Sat, 4 Apr 2009 00:22:44 +0000 Subject: Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4. This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge). Reviewed by: grehan --- sys/powerpc/include/spr.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'sys/powerpc/include/spr.h') diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index 826c2fa30007..eb07208f3695 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -43,6 +43,44 @@ ( { register_t val; \ __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ val; } ) + +/* The following routines allow manipulation of the full 64-bit width + * of SPRs on 64 bit CPUs in bridge mode */ + +#define mtspr64(reg,valhi,vallo,scratch) \ + __asm __volatile(" \ + mfmsr %0; \ + insrdi %0,1,1,0; \ + mtmsrd %0; \ + isync; \ + \ + sld %1,%1,%4; \ + or %1,%1,%2; \ + mtspr %3,%1; \ + srd %1,%1,%4; \ + \ + clrldi %0,%0,1; \ + mtmsrd %0; \ + isync;" \ + : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32)) + +#define mfspr64upper(reg,scratch) \ + ( { register_t val; \ + __asm __volatile(" \ + mfmsr %0; \ + insrdi %0,1,1,0; \ + mtmsrd %0; \ + isync; \ + \ + mfspr %1,%2; \ + srd %1,%1,%3; \ + \ + clrldi %0,%0,1; \ + mtmsrd %0; \ + isync;" \ + : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32)); \ + val; } ) + #endif /* _LOCORE */ /* @@ -112,7 +150,11 @@ #define IBM401E2 0x0025 #define IBM401F2 0x0026 #define IBM401G2 0x0027 +#define IBM970 0x0039 +#define IBM970FX 0x003c #define IBMPOWER3 0x0041 +#define IBM970MP 0x0044 +#define IBM970GX 0x0045 #define MPC860 0x0050 #define MPC8240 0x0081 #define IBM405GP 0x4011 -- cgit v1.2.3