From 1455de177527afa7d96b22b0eca618557b7c18b9 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sat, 16 Jul 2011 00:30:23 +0000 Subject: The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan --- sys/mips/malta/gt_pci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'sys/mips/malta') diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c index 237e74227e0e..aa28639fada1 100644 --- a/sys/mips/malta/gt_pci.c +++ b/sys/mips/malta/gt_pci.c @@ -326,15 +326,15 @@ gt_pci_attach(device_t dev) ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_RR); /* reset, program device, 4 bytes */ @@ -348,15 +348,15 @@ gt_pci_attach(device_t dev) ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_RR); /* -- cgit v1.2.3