From 7420e9dc9da7794308f2f6b9f49aadde8f1fc59c Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Fri, 26 Feb 2010 19:18:29 +0000 Subject: Don't hardcod register offset to set PCIe max read request size. The register offset is not valid on 88E8072 controller. Also don't blindly increase max read request size to 4096, instead, use 2048 which seems to be more sane value and only change the value if the hardware default size(512) was used on that register. For PCIX controllers, use system defined constant rather than using magic value. While I'm here stop showing negotiated link width. --- sys/dev/msk/if_msk.c | 47 ++++++++++++++++++----------------------------- sys/dev/msk/if_mskreg.h | 2 ++ 2 files changed, 20 insertions(+), 29 deletions(-) (limited to 'sys/dev/msk') diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index 0d141d1b68a5..9c61187e0896 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -1356,35 +1356,22 @@ mskc_reset(struct msk_softc *sc) * On dual port PCI-X card, there is an problem where status * can be received out of order due to split transactions. */ - if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { - int pcix; + if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { uint16_t pcix_cmd; - if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { - pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); - /* Clear Max Outstanding Split Transactions. */ - pcix_cmd &= ~0x70; - CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); - pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); - CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); - } + pcix_cmd = pci_read_config(sc->msk_dev, + sc->msk_pcixcap + PCIXR_COMMAND, 2); + /* Clear Max Outstanding Split Transactions. */ + pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; + CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); + pci_write_config(sc->msk_dev, + sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); + CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); } - if (sc->msk_bustype == MSK_PEX_BUS) { - uint16_t v, width; - - v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); - /* Change Max. Read Request Size to 4096 bytes. */ - v &= ~PEX_DC_MAX_RRS_MSK; - v |= PEX_DC_MAX_RD_RQ_SIZE(5); - pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); - width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); - width = (width & PEX_LS_LINK_WI_MSK) >> 4; - v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); - v = (v & PEX_LS_LINK_WI_MSK) >> 4; - if (v != width) - device_printf(sc->msk_dev, - "negotiated width of link(x%d) != " - "max. width of link(x%d)\n", width, v); + if (sc->msk_expcap != 0) { + /* Change Max. Read Request Size to 2048 bytes. */ + if (pci_get_max_read_req(sc->msk_dev) == 512) + pci_set_max_read_req(sc->msk_dev, 2048); } /* Clear status list. */ @@ -1694,11 +1681,13 @@ mskc_attach(device_t dev) } /* Check bus type. */ - if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) + if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { sc->msk_bustype = MSK_PEX_BUS; - else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) + sc->msk_expcap = reg; + } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { sc->msk_bustype = MSK_PCIX_BUS; - else + sc->msk_pcixcap = reg; + } else sc->msk_bustype = MSK_PCI_BUS; switch (sc->msk_hw_id) { diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 75056b6265a0..e528e332dfbe 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -2476,6 +2476,8 @@ struct msk_softc { uint8_t msk_hw_rev; uint8_t msk_bustype; uint8_t msk_num_port; + int msk_expcap; + int msk_pcixcap; int msk_ramsize; /* amount of SRAM on NIC */ uint32_t msk_pmd; /* physical media type */ uint32_t msk_intrmask; -- cgit v1.2.3