From 389c8bd51ead1f1c111e8f8baad65762f6823ff4 Mon Sep 17 00:00:00 2001 From: Gavin Atkinson Date: Tue, 18 Sep 2012 22:04:59 +0000 Subject: Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week --- sys/dev/alc/if_alc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'sys/dev/alc') diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c index c73075c6a8fc..2a0ddb2f509b 100644 --- a/sys/dev/alc/if_alc.c +++ b/sys/dev/alc/if_alc.c @@ -683,7 +683,7 @@ alc_aspm(struct alc_softc *sc, int media) if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == (ALC_FLAG_APS | ALC_FLAG_PCIE)) linkcfg = CSR_READ_2(sc, sc->alc_expcap + - PCIR_EXPRESS_LINK_CTL); + PCIER_LINK_CTL); else linkcfg = 0; pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; @@ -698,7 +698,7 @@ alc_aspm(struct alc_softc *sc, int media) if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && sc->alc_rev == ATHEROS_AR8152_B_V10) linkcfg |= 0x80; - CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, + CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, linkcfg); pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | PM_CFG_HOTRST); @@ -798,10 +798,10 @@ alc_attach(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; - burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); + burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); sc->alc_dma_rd_burst = - (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; - sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; + (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; + sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; if (bootverbose) { device_printf(dev, "Read request size : %u bytes.\n", alc_dma_burst[sc->alc_dma_rd_burst]); @@ -831,9 +831,9 @@ alc_attach(device_t dev) CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); } /* Disable ASPM L0S and L1. */ - cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { - ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); + cap = CSR_READ_2(sc, base + PCIER_LINK_CAP); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { + ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL); if ((ctl & 0x08) != 0) sc->alc_rcb = DMA_CFG_RCB_128; if (bootverbose) -- cgit v1.2.3