From 4c024bbdf85e2dda152c1a0cd25bbc695e32b694 Mon Sep 17 00:00:00 2001 From: KATO Takenori Date: Sat, 22 Mar 1997 18:54:54 +0000 Subject: Improved CPU identification and initialization routines. This supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD) Nx586 CPU, and initialize special registers of Cyrix CPU and msr of IBM Blue Lightning CPU. If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in write-through mode. This can be disabled by kernel configuration options. Reviewed by: Bruce Evans and Jordan K. Hubbard --- sys/conf/files.pc98 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'sys/conf/files.pc98') diff --git a/sys/conf/files.pc98 b/sys/conf/files.pc98 index 37cf0a937ba6..b5c3dce8f184 100644 --- a/sys/conf/files.pc98 +++ b/sys/conf/files.pc98 @@ -3,7 +3,7 @@ # # modified for PC-9801 # -# $Id: files.pc98,v 1.16 1997/02/22 09:43:22 peter Exp $ +# $Id: files.pc98,v 1.17 1997/03/19 16:14:25 kato Exp $ # aic7xxx_asm optional ahc device-driver \ dependency "$S/dev/aic7xxx/*.[chyl]" \ @@ -49,6 +49,7 @@ i386/i386/i386-gdbstub.c optional ddb i386/i386/exception.s standard i386/i386/identcpu.c standard i386/i386/in_cksum.c optional inet +i386/i386/initcpu.c standard # locore.s needs to be handled in Makefile to put it first. Otherwise it's # now normal. # i386/i386/locore.s standard -- cgit v1.2.3